Dumping Memory map: 00 00000000 - 0009f000: Free memory Dumping Memory map: 00 00000000 - 0009f000: Free memory 01 0009f000 - 000a0000: FirmwarePermanent Dumping Memory map: 00 00000000 - 0009f000: Free memory 01 0009f000 - 000a0000: FirmwarePermanent 02 000f0000 - 00100000: FirmwarePermanent Dumping Memory map: 00 00000000 - 0009f000: Free memory 01 0009f000 - 000a0000: FirmwarePermanent 02 000f0000 - 00100000: FirmwarePermanent 03 00100000 - 3fff0000: Free memory Dumping Memory map: 00 00000000 - 0009f000: Free memory 01 0009f000 - 000a0000: FirmwarePermanent 02 000f0000 - 00100000: FirmwarePermanent 03 00100000 - 3fff0000: Free memory 04 3fff0000 - 40000000: SpecialMemory Dumping Memory map: 00 00000000 - 0009f000: Free memory 01 0009f000 - 000a0000: FirmwarePermanent 02 000f0000 - 00100000: FirmwarePermanent 03 00100000 - 3fff0000: Free memory 04 3fff0000 - 40000000: SpecialMemory 05 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 0009f000: Free memory 02 0009f000 - 000a0000: FirmwarePermanent 03 000f0000 - 00100000: FirmwarePermanent 04 00100000 - 3fff0000: Free memory 05 3fff0000 - 40000000: SpecialMemory 06 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 0009f000: Free memory 02 0009f000 - 000a0000: FirmwarePermanent 03 000a0000 - 000f0000: FirmwarePermanent 04 000f0000 - 00100000: FirmwarePermanent 05 00100000 - 3fff0000: Free memory 06 3fff0000 - 40000000: SpecialMemory 07 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 0009f000: Free memory 02 0009f000 - 000a0000: FirmwarePermanent 03 000a0000 - 000f0000: FirmwarePermanent 04 000f0000 - 00100000: SpecialMemory 05 00100000 - 3fff0000: Free memory 06 3fff0000 - 40000000: SpecialMemory 07 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 0009f000: Free memory 02 0009f000 - 000a0000: FirmwarePermanent 03 000a0000 - 000f0000: FirmwarePermanent 04 000f0000 - 00100000: SpecialMemory 05 00100000 - 00fff000: Free memory 06 00fff000 - 01000000: SpecialMemory 07 01000000 - 3fff0000: Free memory 08 3fff0000 - 40000000: SpecialMemory 09 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 00007000: FirmwareTemporary 02 00007000 - 0009f000: Free memory 03 0009f000 - 000a0000: FirmwarePermanent 04 000a0000 - 000f0000: FirmwarePermanent 05 000f0000 - 00100000: SpecialMemory 06 00100000 - 00fff000: Free memory 07 00fff000 - 01000000: SpecialMemory 08 01000000 - 3fff0000: Free memory 09 3fff0000 - 40000000: SpecialMemory 10 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 00007000: FirmwareTemporary 02 00007000 - 0000f000: OsloaderStack 03 0000f000 - 0009f000: Free memory 04 0009f000 - 000a0000: FirmwarePermanent 05 000a0000 - 000f0000: FirmwarePermanent 06 000f0000 - 00100000: SpecialMemory 07 00100000 - 00fff000: Free memory 08 00fff000 - 01000000: SpecialMemory 09 01000000 - 3fff0000: Free memory 10 3fff0000 - 40000000: SpecialMemory 11 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 00007000: FirmwareTemporary 02 00007000 - 0000f000: OsloaderStack 03 0000f000 - 00064000: LoadedProgram 04 00064000 - 0009f000: Free memory 05 0009f000 - 000a0000: FirmwarePermanent 06 000a0000 - 000f0000: FirmwarePermanent 07 000f0000 - 00100000: SpecialMemory 08 00100000 - 00fff000: Free memory 09 00fff000 - 01000000: SpecialMemory 10 01000000 - 3fff0000: Free memory 11 3fff0000 - 40000000: SpecialMemory 12 fffc0000 - 00000000: FirmwarePermanent Dumping Memory map: 00 00000000 - 00001000: FirmwarePermanent 01 00001000 - 00007000: FirmwareTemporary 02 00007000 - 0000f000: OsloaderStack 03 0000f000 - 00064000: LoadedProgram 04 00064000 - 00074000: FirmwareTemporary 05 00074000 - 0009f000: Free memory 06 0009f000 - 000a0000: FirmwarePermanent 07 000a0000 - 000f0000: FirmwarePermanent 08 000f0000 - 00100000: SpecialMemory 09 00100000 - 00fff000: Free memory 10 00fff000 - 01000000: SpecialMemory 11 01000000 - 3fff0000: Free memory 12 3fff0000 - 40000000: SpecialMemory 13 fffc0000 - 00000000: FirmwarePermanent (../../ntoskrnl/kd/kdio.c:376) ----------------------------------------------------- (../../ntoskrnl/kd/kdio.c:377) ReactOS 0.4-SVN (Build 20150129-r66105) (../../ntoskrnl/kd/kdio.c:379) 1 System Processor [1023 MB Memory] (../../ntoskrnl/kd/kdio.c:380) Command Line: DEBUG DEBUGPORT=COM1 BAUDRATE=115200 SOS MININT (../../ntoskrnl/kd/kdio.c:384) ARC Paths: multi(0)disk(0)cdrom(96) \ multi(0)disk(0)cdrom(96) \reactos\ (../../ntoskrnl/ke/i386/cpu.c:494) Supported CPU features : KF_V86_VIS KF_RDTSC KF_CR4 KF_CMOV KF_GLOBAL_PAGE KF_LARGE_PAGE KF_MTRR KF_CMPXCHG8B KF_MMX KF_WORKING_PTE KF_PAT KF_FXSR KF_FAST_SYSCALL KF_XMMI KF_3DNOW KF_XMMI64 (../../ntoskrnl/ke/i386/cpu.c:801) Prefetch Cache: 64 bytes L2 Cache: 524288 bytes L2 Cache Line: 64 bytes L2 Cache Associativity: 16 (../../ntoskrnl/mm/ARM3/mminit.c:1443) HAL I/O Mapping at FFFE0000 is unsafe (../../ntoskrnl/mm/mminit.c:260) 0x80000000 - 0x83000000 Boot Loaded Image (../../ntoskrnl/mm/mminit.c:264) 0xB0000000 - 0xB0700000 PFN Database (../../ntoskrnl/mm/mminit.c:268) 0xB0700000 - 0xB26C8000 ARM3 Non Paged Pool (../../ntoskrnl/mm/mminit.c:272) 0xB9400000 - 0xBB400000 System View Space (../../ntoskrnl/mm/mminit.c:276) 0xBB400000 - 0xC0000000 Session Space (../../ntoskrnl/mm/mminit.c:279) 0xC0000000 - 0xC03FFFFF Page Tables (../../ntoskrnl/mm/mminit.c:282) 0xC0300000 - 0xC0300FFF Page Directories (../../ntoskrnl/mm/mminit.c:285) 0xC0400000 - 0xC07FFFFF Hyperspace (../../ntoskrnl/mm/mminit.c:289) 0xE1000000 - 0xECC00000 ARM3 Paged Pool (../../ntoskrnl/mm/mminit.c:292) 0xECC00000 - 0xF7BE0000 System PTE Space (../../ntoskrnl/mm/mminit.c:295) 0xF7BE0000 - 0xFFBE0000 Non Paged Pool Expansion PTE Space (../../ntoskrnl/config/cmcheck.c:25) CmCheckRegistry(0xB2470008, 2) is UNIMPLEMENTED! (../../hal/halx86/legacy/bussupp.c:594) Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail! (../../hal/halx86/legacy/bussupp.c:623) Found parent bus (indicating PCI Bridge). PCI devices may fail! ====== PCI BUS HARDWARE DETECTION ======= 00:02.0 VGA compatible controller [0300]: InnoTek Systemberatung GmbH VirtualBox Graphics Adapter [80ee:beef] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at e0000000 (32-bit, prefetchable) [size=512M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 00:03.0 Ethernet controller [0200]: Advanced Micro Devices, Inc. [AMD] 79c970 [PCnet32 LANCE] [1022:2000] (rev 40) Subsystem: PCnet - Fast 79C971 [1022:2000] Flags: bus master, medium devsel, latency 0, IRQ 09 I/O ports at d000 [size=4K] Memory at f0000000 (32-bit, non-prefetchable) [size=256M] Device is using IRQ 9! ISA Cards using that IRQ may fail! 00:04.0 System peripheral [0880]: InnoTek Systemberatung GmbH VirtualBox Guest Service [80ee:cafe] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 05 I/O ports at d020 [size=32] Memory at f0400000 (32-bit, non-prefetchable) [size=4M] Memory at f0800000 (32-bit, prefetchable) [size=8M] Device is using IRQ 5! ISA Cards using that IRQ may fail! 00:05.0 Multimedia audio controller [0401]: Intel Corporation 82801AA AC'97 Audio Controller [8086:2415] (rev 01) Subsystem: Terminator 2x/i [8086:0000] Flags: bus master, medium devsel, latency 0, IRQ 11 I/O ports at d100 [size=256] I/O ports at d200 [size=512] Device is using IRQ 11! ISA Cards using that IRQ may fail! 00:07.0 Secondary bus towards host CPU [0680]: Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] (rev 08) Subsystem: Unknown [0000:0000] Flags: bus master, medium devsel, latency 0, IRQ 09 Device is using IRQ 9! ISA Cards using that IRQ may fail! 00:18.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev f2) Subsystem: Unknown [0000:0000] Flags: bus master, 66MHz, fast devsel, latency 0 Memory at 00010100 (32-bit, non-prefetchable) [size=256] Memory at 0000dfe0 (32-bit, non-prefetchable) [size=256] Memory at f08ff090 (32-bit, non-prefetchable) [size=4K] Memory at 0000fff0 (32-bit, non-prefetchable) [size=256] 00:19.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev f2) Subsystem: Unknown [0000:0000] Flags: bus master, 66MHz, fast devsel, latency 0 Memory at 00020200 (32-bit, non-prefetchable) [size=512] Memory at 0000dfe0 (32-bit, non-prefetchable) [size=256] Memory at f08ff090 (32-bit, non-prefetchable) [size=4K] Memory at 0000fff0 (32-bit, non-prefetchable) [size=256] 00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 02) Subsystem: Unknown [8086:7270] Flags: bus master, medium devsel, latency 0 00:1f.1 IDE interface [0101]: Intel Corporation 631xESB/632xESB IDE Controller [8086:269e] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0 I/O ports at e000 [size=8K] 00:1f.2 SATA controller [0106]: Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode] [8086:2829] (rev 02) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 09 I/O ports at e010 [size=16] I/O ports at e018 [size=8] I/O ports at e020 [size=32] I/O ports at e028 [size=8] I/O ports at e030 [size=16] Memory at f0900000 (32-bit, non-prefetchable) [size=1M] Device is using IRQ 9! ISA Cards using that IRQ may fail! 00:1f.4 USB controller [0c03]: Apple Inc. KeyLargo/Intrepid USB [106b:003f] (rev 00) Subsystem: GLoria L [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 09 Memory at f0902000 (32-bit, non-prefetchable) [size=8K] Device is using IRQ 9! ISA Cards using that IRQ may fail! Device is an OHCI (USB) PCI Expansion Card. Turn off Legacy USB in your BIOS! 00:1f.5 USB controller [0c03]: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 09 Memory at f0903000 (32-bit, non-prefetchable) [size=4K] Device is using IRQ 9! ISA Cards using that IRQ may fail! Device is an Intel UHCI (USB) Controller. Turn off Legacy USB in your BIOS! ====== PCI BUS DETECTION COMPLETE ======= PC Compatible Eisa/Isa HAL Detected (../../ntoskrnl/io/iomgr/driver.c:1630) '\Driver\SACDRV' initialization failed, status (0xc0000037) (../../ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\SACDRV' ATAPI IDE MiniPort Driver (UniATA) v 0.45e Parameter PrintLogo Parameter PrintLogo = 0x0 UniATA Init: OS should be ReactOS UniATA Init: OS ver 4.1 (1), 1 CPU(s) Performance calibration: dt=14995, counter=2495279 InitBadBlocks general InitBadBlocks returned: 0xc0000034 UniataInitAtaCommands: Parameter SkipRaids Parameter SkipRaids = 0x1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 Parameter LogToDisplay Parameter LogToDisplay = 0x0 HwInitializationDataSize = 50 set NeedPhysicalAddresses = TRUE set AtapiAdapterControl() ptr ATAPI IDE enum supported BusMaster Devices Parameter VirtualMachineType Parameter VirtualMachineType = 0x0 Parameter VirtualBox Parameter VirtualBox = 0x0 -- BusID: 0x0:0x4:0x0 - VirtualBox Guest Service -- BusID: 0x0:0x1f:0x1 Storage Class DevId = 269E8086 Class = 0001/0001, ProgIf 8A Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 Default device found, pass 0 InterruptPin = 0x0 InterruptLine = 0x0 Enabling Mem/Io spaces and busmastering... Initial pciData.Command = 0x7 PCI_ENABLE_IO_SPACE PCI_ENABLE_MEMORY_SPACE PCI_ENABLE_BUS_MASTER InterruptLine = 0x0 Final pciData.Command = 0x7 Range 4 = 0xe001 count: BMListLen++ -- BusID: 0x0:0x1f:0x2 Storage Class DevId = 28298086 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 Default device found, pass 0 InterruptPin = 0x1 InterruptLine = 0x9 Enabling Mem/Io spaces and busmastering... Initial pciData.Command = 0x7 PCI_ENABLE_IO_SPACE PCI_ENABLE_MEMORY_SPACE PCI_ENABLE_BUS_MASTER InterruptLine = 0x9 Final pciData.Command = 0x7 Range 0 = 0xe011 Range 1 = 0xe019 Range 2 = 0xe021 Range 3 = 0xe029 Range 4 = 0xe031 Range 5 = 0xf0900000 count: BMListLen++ -- BusID: 0x0:0x4:0x0 - VirtualBox Guest Service -- BusID: 0x0:0x1f:0x1 Storage Class DevId = 269E8086 Class = 0001/0001, ProgIf 8A Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 Default device found, pass 1 InterruptPin = 0x0 InterruptLine = 0x0 Range 4 = 0xe001 found suitable device Parameter NativePCIMode Parameter NativePCIMode = 0x0 Add to BMList, AltInit 0 -- BusID: 0x0:0x1f:0x2 Storage Class DevId = 28298086 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 Default device found, pass 1 InterruptPin = 0x1 InterruptLine = 0x9 Range 0 = 0xe011 Range 1 = 0xe019 Range 2 = 0xe021 Range 3 = 0xe029 Range 4 = 0xe031 Range 5 = 0xf0900000 found suitable device -- BusID: 0x0:0x4:0x0 - VirtualBox Guest Service -- BusID: 0x0:0x1f:0x1 Storage Class DevId = 269E8086 Class = 0001/0001, ProgIf 8A Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 Default device found, pass 2 InterruptPin = 0x0 InterruptLine = 0x0 Range 4 = 0xe001 found suitable device -- BusID: 0x0:0x1f:0x2 Storage Class DevId = 28298086 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 Default device found, pass 2 InterruptPin = 0x1 InterruptLine = 0x9 Range 0 = 0xe011 Range 1 = 0xe019 Range 2 = 0xe021 Range 3 = 0xe029 Range 4 = 0xe031 Range 5 = 0xf0900000 found suitable device Add to BMList, AltInit 0 BMListLen=2 adjust options for VirtualBox Parameter WaitBusyCount Parameter WaitBusyCount = 0x4e20 Parameter WaitBusyDelay Parameter WaitBusyDelay = 0x96 Parameter WaitDrqDelay Parameter WaitDrqDelay = 0x64 Parameter WaitBusyLongCount Parameter WaitBusyLongCount = 0x4e20 Parameter WaitBusyLongDelay Parameter WaitBusyLongDelay = 0xfa Parameter AtapiSendDisableIntr Parameter AtapiSendDisableIntr = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x0 Parameter MaxIsrWait Parameter MaxIsrWait = 0xc8 ATAPI IDE: Look for legacy ISA-bridged PCI IDE controller (onboard) ATAPI IDE: BMListLen 2 Parameter IgnoreIsaCompatiblePci Parameter IgnoreIsaCompatiblePci = 0x0 UniataClaimLegacyPCIIDE: (../../hal/halx86/legacy/bussupp.c:1159) Slot assignment for 5 on bus 0 (../../hal/halx86/legacy/bus/pcibus.c:719) WARNING: PCI Slot Resource Assignment is FOOBAR ok 0x0 Parameter IgnoreIsaCompatiblePci Parameter IgnoreIsaCompatiblePci = 0x0 Try init channel 0, method 0 UniataFindBusMasterController: Context=0, BMListLen=2 ConfigInfo->Length 8c AdapterInterfaceType: Isa bm_offset 0, channel 0 AdapterInterfaceType=0x1 IoBusNumber=0x0 slotNumber=0x3f busDataRead DevId = 269E8086 Class = 0001/0001 Storage Class MasterDev (1) Check exclude Parameter Exclude Parameter Exclude = 0x0 UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0x33 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 i: 0x1f HwFlags: 0x0 Parameter HwFlagsOverride Parameter HwFlagsOverride = 0x0 HwFlagsOverride: 0x0 Parameter HwFlagsAdd Parameter HwFlagsAdd = 0x0 HwFlagsAdd: 0x0 HwFlags (final): 0x0 MaxTransferMode: 0x45 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 MaxTransferMode (overriden): 0x45 UniataChipDetectChannels: MasterDev -> 1 chan Parameter Exclude Parameter Exclude = 0x0 PortMask 0x1 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 mask -> 1 chans Parameter NumberChannels Parameter NumberChannels = 0x1 reg -> 1 chans Final PortMask 0x1 allocate 2 Luns for 1 channels ForceSimplex = 0 HwFlags = 0 (0)HwFlags = 0 (1)HwFlags = 0 (2)found suitable device HwFlags = 0 (3)Range 4 = 0xe001 IsBusMaster == TRUE AtapiGetIoRange: AtapiGetIoRange: rid 0x4, start 0x0, offs 0x0, len 0x8, mem 0x0 AtapiGetIoRange: (2) 0xe000 BusMasterAddress (base): 0xe000 AtapiReadChipConfig: devExt 0xb246c44c AtapiReadChipConfig: dev 0x0, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x45 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 MaxTransferMode (overriden): 0x45 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x0 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x0, ph chan -2, c -1 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 re-enable IO resources of MasterDev Enabling Mem/Io spaces and busmastering... Initial pciData.Command = 0x7 PCI_ENABLE_IO_SPACE PCI_ENABLE_MEMORY_SPACE PCI_ENABLE_BUS_MASTER InterruptLine = 0x0 Final pciData.Command = 0x7 AtapiChipInit: dev 0x0, ph chan 0, c 0 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 intel 80-pin check (reg54=4f0) simplexOnly = 0 (2)MasterDev (2) 1 channels & 1 irq for 1 controller update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 0 chan[0] InterruptMode: 1, Level 14, Level2 0, Vector 0, Vector2 0 Reconstruct ConfigInfo BMList[i].channel 0x0, NumberChannels 0x1, channel 0x0 de 0xb246c44c, Channel 0x0 chan = 0xb246b008 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb246b008 Lun 0x0 Lun ptr 0xb2695008 Lun 0x1 Lun ptr 0xb2695310 AtapiReadChipConfig: devExt 0xb246c44c AtapiReadChipConfig: dev 0x0, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 MaxTransferMode (overriden): 0x45 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 set AccessRanges Getting IO ranges IO range 1 0x1f0 IO range 2 0x3f6 IDX_IO1 0->1f0(io) IDX_IO2 10->3f6(io) IDX_BM_IO 14->e000(io) IDX_SATA_IO 19->0(io) AltStatus (0x50) Reg_0x1 (0x1f1) = 0x0 Reg_0x2 (0x1f2) = 0x1 Reg_0x3 (0x1f3) = 0x1 Reg_0x4 (0x1f4) = 0x0 Reg_0x5 (0x1f5) = 0x0 Reg_0x6 (0x1f6) = 0xe0 Reg_0x7 (0x1f7) = 0x50 BM_0x0 (0xe000) = 0x0 BM_0x1 (0xe001) = 0xff BM_0x2 (0xe002) = 0x20 BM_0x3 (0xe003) = 0xff clean IDE intr 0 clean IDE intr 1 DMA status 0x20 claim Compatible controller claim Primary AtapiDmaAlloc: allocate tmp buffers below 4Gb AtapiVirtToPhysAddr_: b246b800 -> 00000000:04d6b800 AtapiVirtToPhysAddr_: b244b000 -> 00000000:04d4b000 exit: init spinlock MasterDev=0x1, NumberChannels=0x1, Isr2DevObj=0xb246cd40 Init ISR: Unnecessary MasterDev=0x1, NumberChannels=0x1, Isr2DevObj=0xb246cd40 do not tell system, that we know about PCI IO ranges final chan[1] InterruptMode: 1, Level 14, Level2 0, Vector 0, Vector2 0 return SP_RETURN_FOUND Attempt 0 of MasterDev ok (../../ntoskrnl/io/iomgr/iorsrce.c:874) IoReportResourceUsage is halfplemented! AtapiHwInitialize: (base) mark chan 0 of master controller [0] as inited AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 re-enable IO resources of MasterDev Enabling Mem/Io spaces and busmastering... Initial pciData.Command = 0x7 PCI_ENABLE_IO_SPACE PCI_ENABLE_MEMORY_SPACE PCI_ENABLE_BUS_MASTER InterruptLine = 0x0 Final pciData.Command = 0x7 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 intel 80-pin check (reg54=4f0) FindDevices: AtapiDisableInterrupts_0: 0 max_ldev 2 CheckDevice: Device 0x0 CheckDevice: reset dev AtapiSoftReset: statusByte2 50: DMA status 0x20 HDD at home HDD at home CheckDevice: status 0x41 CheckDevice: IDE device check IssueIdentify: Checking for IDE. Status (0x50) AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x20000 count 0x0 feature 0x0 IssueIdentify: IDE_STATUS_DRQ (0x58) IssueIdentify: Status before read words 0x58 IssueIdentify: statusByte 0x58 IssueIdentify: BASE statusByte 0x58 use 16bit IO IssueIdentify: suck data port IssueIdentify: statusByte 0x50 IssueIdentify: statusByte 0x50 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV51f46fc7c-71ff05 4 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 4/7f SATA: 0 SATA support: 0, CAPs 0x0 OrigTransferMode: 46, Active: 42 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode Use IDE_COMMAND_READ_NATIVE_SIZE AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 count 0x0 feature 0x0 Status 0x40 NativeNumOfSectors 0x13fffff Use IDE_COMMAND_SET_NATIVE_SIZE Update NumOfSectors to 0x13fffff AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xf9, lba 0x13fffff count 0x0 feature 0x0 Status 0x41 requested LunExt->GeomType=ffffffff tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2695008 S/N:VBOX_HARDDISK___________________________-VB154ff67c-c17ff504_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x41) CheckDevice: Device 0x0 is IDE CheckDevice: check status: found CheckDevice: Device 0x1 CheckDevice: reset dev AtapiSoftReset: statusByte2 41: DMA status 0x20 HDD at home HDD at home CheckDevice: status 0x0 CheckDevice: IDE device check IssueIdentify: Checking for IDE. Status (0x0) IssueIdentify: statusByte != IDE_STATUS_IDLE IssueIdentify: no dev (dev 1) CheckDevice: check status: not found FindDevices: select 0 dev to clear INTR FindDevices: statusByte=0x41 FindDevices: select 1 dev to clear INTR FindDevices: statusByte=0x0 FindDevices: select 0 dev on exit AtapiEnableInterrupts_0: 1 FindDevices: returning 1 AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 AtapiHwInitialize: IDE branch AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 count 0x80 feature 0x0 Status 0x40 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 128 Try Enable Read Cache AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 count 0x0 feature 0xaa Status 0x50 Try Enable Write Cache AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 count 0x0 feature 0x2 Status 0x50 Try Enable Adv. Power Mgmt AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 count 0x80 feature 0x5 Status 0x41 AtapiHwInitialize: Enable APM on Device 0 failed try mode 0x45 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x45 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x5 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 Setup chip a:w:u=4:2:5 AtaSetTransferMode: Set 0x45 on Device 0/0 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 count 0x45 feature 0x3 Status 0x50 Using 0x45 mode AtapiEnableInterrupts_0: 1 AtapiHwInitialize: lChannel 0x0, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784cf90, CDB 0xf784cfc0, AtaReq 0xb2684000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf784cf90 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784cc78 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784cf90 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b246b008, f784cf90) AtapiStartIo: UniataRemoveRequest(b246b008, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b246b008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 VendorID+DeviceID/Rev 0x269e8086/0x0 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf784cf90 TopLevel (3), AtaReq 0xb2684000 HDD at home CheckDevice: Device 0x1 CheckDevice: reset dev AtapiSoftReset: statusByte2 0: DMA status 0x20 HDD at home HDD at home CheckDevice: status 0x0 CheckDevice: IDE device check IssueIdentify: Checking for IDE. Status (0x0) IssueIdentify: statusByte != IDE_STATUS_IDLE IssueIdentify: no dev (dev 1) CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b246b008, f784cf90) AtapiStartIo: UniataRemoveRequest(b246b008, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b246b008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf784cf90 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request ScsiPortInitialize Status 0x0 Parameter IgnoreIsaCompatiblePci Parameter IgnoreIsaCompatiblePci = 0x0 Try init channel 1, method 0 UniataFindBusMasterController: Context=0, BMListLen=2 ConfigInfo->Length 8c AdapterInterfaceType: Isa bm_offset 8, channel 1 AdapterInterfaceType=0x1 IoBusNumber=0x0 slotNumber=0x3f busDataRead DevId = 269E8086 Class = 0001/0001 Storage Class MasterDev (1) Check exclude Parameter Exclude Parameter Exclude = 0x0 UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0x33 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 i: 0x1f HwFlags: 0x0 Parameter HwFlagsOverride Parameter HwFlagsOverride = 0x0 HwFlagsOverride: 0x0 Parameter HwFlagsAdd Parameter HwFlagsAdd = 0x0 HwFlagsAdd: 0x0 HwFlags (final): 0x0 MaxTransferMode: 0x45 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 MaxTransferMode (overriden): 0x45 UniataChipDetectChannels: MasterDev -> 1 chan Parameter Exclude Parameter Exclude = 0x0 PortMask 0x1 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 mask -> 1 chans Parameter NumberChannels Parameter NumberChannels = 0x1 reg -> 1 chans Final PortMask 0x1 allocate 2 Luns for 1 channels ForceSimplex = 0 HwFlags = 0 (0)HwFlags = 0 (1)HwFlags = 0 (2)found suitable device HwFlags = 0 (3)Range 4 = 0xe001 IsBusMaster == TRUE AtapiGetIoRange: AtapiGetIoRange: rid 0x4, start 0x0, offs 0x8, len 0x8, mem 0x0 AtapiGetIoRange: (2) 0xe008 BusMasterAddress (base): 0xe008 AtapiReadChipConfig: devExt 0xb26837ec AtapiReadChipConfig: dev 0x0, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x45 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 MaxTransferMode (overriden): 0x45 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x0 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x0, ph chan -2, c -1 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 re-enable IO resources of MasterDev Enabling Mem/Io spaces and busmastering... Initial pciData.Command = 0x7 PCI_ENABLE_IO_SPACE PCI_ENABLE_MEMORY_SPACE PCI_ENABLE_BUS_MASTER InterruptLine = 0x0 Final pciData.Command = 0x7 AtapiChipInit: dev 0x0, ph chan 0, c 0 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 intel 80-pin check (reg54=14f1) simplexOnly = 0 (2)MasterDev (2) 1 channels & 1 irq for 1 controller update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 0 chan[1] InterruptMode: 1, Level 15, Level2 0, Vector 0, Vector2 0 Reconstruct ConfigInfo BMList[i].channel 0x1, NumberChannels 0x1, channel 0x1 de 0xb26837ec, Channel 0x1 chan = 0xb2682008 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb2682008 Lun 0x0 Lun ptr 0xb2448008 Lun 0x1 Lun ptr 0xb2448310 AtapiReadChipConfig: devExt 0xb26837ec AtapiReadChipConfig: dev 0x0, ph chan 1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 MaxTransferMode (overriden): 0x45 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x45 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 set AccessRanges Getting IO ranges IO range 1 0x170 IO range 2 0x376 IDX_IO1 0->170(io) IDX_IO2 10->376(io) IDX_BM_IO 14->e008(io) IDX_SATA_IO 19->0(io) AltStatus (0x50) Reg_0x1 (0x171) = 0x0 Reg_0x2 (0x172) = 0x53 Reg_0x3 (0x173) = 0xaa Reg_0x4 (0x174) = 0x0 Reg_0x5 (0x175) = 0x8 Reg_0x6 (0x176) = 0xa0 Reg_0x7 (0x177) = 0x50 BM_0x0 (0xe008) = 0x0 BM_0x1 (0xe009) = 0xff BM_0x2 (0xe00a) = 0x20 BM_0x3 (0xe00b) = 0xff clean IDE intr 0 clean IDE intr 1 DMA status 0x20 claim Compatible controller claim Secondary AtapiDmaAlloc: allocate tmp buffers below 4Gb AtapiVirtToPhysAddr_: b2682800 -> 00000000:04f82800 AtapiVirtToPhysAddr_: b2428000 -> 00000000:04d28000 exit: init spinlock MasterDev=0x1, NumberChannels=0x1, Isr2DevObj=0xb246cd40 Init ISR: Unnecessary MasterDev=0x1, NumberChannels=0x1, Isr2DevObj=0xb246cd40 do not tell system, that we know about PCI IO ranges final chan[2] InterruptMode: 1, Level 15, Level2 0, Vector 0, Vector2 0 return SP_RETURN_FOUND Attempt 0 of MasterDev ok (../../ntoskrnl/io/iomgr/iorsrce.c:874) IoReportResourceUsage is halfplemented! AtapiHwInitialize: (base) mark chan 1 of master controller [0] as inited AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 re-enable IO resources of MasterDev Enabling Mem/Io spaces and busmastering... Initial pciData.Command = 0x7 PCI_ENABLE_IO_SPACE PCI_ENABLE_MEMORY_SPACE PCI_ENABLE_BUS_MASTER InterruptLine = 0x0 Final pciData.Command = 0x7 AtapiChipInit: dev 0xffffffff, ph chan 1, c 0 HwFlags: 0x0 VendorID/DeviceID/Rev 0x8086/0x269e/0x0 intel 80-pin check (reg54=14f1) FindDevices: AtapiDisableInterrupts_0: 0 max_ldev 2 CheckDevice: Device 0x0 CheckDevice: reset dev AtapiSoftReset: statusByte2 50: DMA status 0x20 ATAPI at home ATAPI at home CheckDevice: status 0x0 CheckDevice: ATAPI signature found IssueIdentify: Checking for ATAPI. Status (0x0) IssueIdentify: Checking for ATAPI (2). Status (0x0) AtaCommand48: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x20000 count 0x0 feature 0x0 IssueIdentify: IDE_STATUS_DRQ (0x58) IssueIdentify: Status before read words 0x58 IssueIdentify: statusByte 0x58 IssueIdentify: BASE statusByte 0x58 use 16bit IO IssueIdentify: suck data port IssueIdentify: statusByte 0x50 IssueIdentify: statusByte 0x50 IssueIdentify: Status after read words 0x50 Model: BVXOC -DOR M FW: .1 0 S/N: BV-210073067 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 4/7f SATA: 0 SATA support: 0, CAPs 0x0 OrigTransferMode: 46, Active: 42 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 InitBadBlocks local LunExt 0xb2448008 S/N:VBOX_CD-ROM_____________________________-VB2-01700376________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: final Status on exit (0x50) CheckDevice: Device 0x0 is ATAPI CheckDevice: check status: found CheckDevice: Device 0x1 CheckDevice: reset dev AtapiSoftReset: statusByte2 50: DMA status 0x20 nobody home! 0x0 != 0x55 FindDevices: select 0 dev to clear INTR FindDevices: statusByte=0x50 FindDevices: select 1 dev to clear INTR FindDevices: statusByte=0x0 FindDevices: select 0 dev on exit AtapiEnableInterrupts_0: 1 FindDevices: returning 1 AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 AtapiHwInitialize: ATAPI/Changer branch try mode 0x45 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x45 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x5 Setup chip a:w:u=4:2:5 AtaSetTransferMode: Set 0x45 on Device 0/0 AtaCommand48: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 count 0x45 feature 0x3 Status 0x50 Using 0x45 mode AtapiEnableInterrupts_0: 1 AtapiHwInitialize: lChannel 0x0, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784cf90, CDB 0xf784cfc0, AtaReq 0xb2417000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf784cf90 TopLevel (3), AtaReq 0xb2417000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: BuildMechanismStatusSrb() MechanismStatusSrb 0xb2682044 AtapiSendCommand: AtapiSendCommand recursive AtapiSendCommand: req state 0x20, Action 3 AtapiSendCommand: prepare..., ATAPI CMD bd (Cdb b2682074) assume IN AtapiSendCommand: use_dma=0, Cmd bd AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiDmaReinit: set PIO mode on Device 0 (45 -> c) AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x45 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0xffffffff Setup chip a:w:u=4:-1:-1 AtaSetTransferMode: Set 0xc on Device 0/0 AtaCommand48: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 count 0xc feature 0x3 Status 0x50 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb b2682074 Command 0xbd to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x58) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiSendCommand: SRB_STATUS_PENDING (2) AtapiStartIo: next Srb f784cf90 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x24 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... ATAPI status 0x58 base status 0x58 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x58) AtapiInterrupt: iReason 2 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 2 AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: get R wordCount 0x4 IdeIntr: Read 0x4 words IdeIntr: PIO Read AtaReq->DataBuffer 0xb2682024, srb->DataBuffer 0xb2682024 status re-check 0x50 AtapiInterrupt: all transferred, AtaReq->WordsLeft == 0 AtapiInterrupt: early complete ? status 50 AtapiInterrupt: CompleteRequest, srbstatus 1 AtapiInterrupt: OriginalSrb != NULL AtapiInterrupt: SCSIOP_MECHANISM_STATUS status 0x1 AtapiSendCommand: req state 0x50, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f784cfc0) assume IN AtapiSendCommand: use_dma=0, Cmd 12 AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f784cfc0 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x80) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiInterrupt: chan->ExpectingInterrupt 1 (1) AtapiInterrupt: send orig SRB_STATUS_PENDING (1) AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... ATAPI status 0x58 base status 0x58 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x58) AtapiInterrupt: iReason 2 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 2 AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: get R wordCount 0x12 IdeIntr: Read 0x12 words IdeIntr: PIO Read AtaReq->DataBuffer 0xf77d9170, srb->DataBuffer 0xf77d9170 status re-check 0x50 AtapiInterrupt: all transferred, AtaReq->WordsLeft == 0 AtapiInterrupt: early complete ? status 50 AtapiInterrupt: CompleteRequest, srbstatus 1 AtapiInterrupt: PIO completion AtapiInterrupt: PIO completion, wait BUSY IdeIntr: ATAPI Read AtaReq->DataBuffer 0xf77d9194, srb->DataBuffer 0xf77d9170, len 0x24 Transfered 2c, full size 24 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xf784cf90, status 1 AtapiInterrupt: RequestComplete, srb 0xf784cf90 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x50 base status 0x50 Unexpected interrupt. OurInterrupt = 2 AtapiInterrupt(base): Catch unexpected AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 VendorID+DeviceID/Rev 0x269e8086/0x0 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf784cf90 TopLevel (3), AtaReq 0xb2417000 nobody home! 0x0 != 0x55 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b2682008, f784cf90) AtapiStartIo: UniataRemoveRequest(b2682008, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2682008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf784cf90 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 VendorID+DeviceID/Rev 0x269e8086/0x0 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request ScsiPortInitialize Status 0x0 Ok, no more retries required !BMList[i].MasterDev ATAPI IDE: Look for PCI IDE controller ATAPI IDE: i 1, BMListLen 2 Parameter IgnoreNativePci Parameter IgnoreNativePci = 0x0 Try init 8086 2829 (../../hal/halx86/legacy/bussupp.c:1159) Slot assignment for 5 on bus 0 (../../hal/halx86/legacy/bus/pcibus.c:719) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=1, BMListLen=2 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0x0 slotNumber=0x5f busDataRead DevId = 28298086 Class = 0001/0006 Storage Class UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0x33 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 i: 0x2a HwFlags: 0x12000000 Parameter HwFlagsOverride Parameter HwFlagsOverride = 0x12000000 HwFlagsOverride: 0x12000000 Parameter HwFlagsAdd Parameter HwFlagsAdd = 0x0 HwFlagsAdd: 0x0 HwFlags (final): 0x12000000 MaxTransferMode: 0x48 Parameter MaxTransferMode Parameter MaxTransferMode = 0x48 MaxTransferMode (overriden): 0x48 UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0xf0900000, offs 0x0, len 0x10, mem 0x1 AtapiGetIoRange: 0xf77d9000 MemIo AHCI Base: 0xf77d9000 MemIo 1 Proc 0 AHCI_0x0 (0xf77d9000) = 0xc8241f80 AHCI_0x4 (0xf77d9004) = 0x80000000 AHCI_0x8 (0xf77d9008) = 0x0 AHCI_0xc (0xf77d900c) = 0x1 AHCI_0x10 (0xf77d9010) = 0x10100 check AHCI mode, GHC 0x80000000 AHCI CAP 0xc8241f80, CAP2 0x0 64bit NCQ CCC AHCI PI 0x1 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 CommandSlots 31 Detected Channels 1 / 1 Adjusted Channels 1 AHCI version 0x1.10 controller with 1 ports (mask 0x1) detected AHCI SATA Gen 2 PM not supported -> 1 lun/chan AHCI detect status 1 allocate 1 Luns for 1 channels Intel chip config: 0 AtapiGetIoRange: AtapiGetIoRange: rid 0x4, start 0xe030, offs 0x0, len 0x8, mem 0x0 AtapiGetIoRange: (2) 0xe030 Intel BM check at e030 BM status: ff invalid BM status, keep AHCI mode ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb24167ec AtapiReadChipConfig: dev 0x1, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x48 Parameter MaxTransferMode Parameter MaxTransferMode = 0x48 MaxTransferMode (overriden): 0x48 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x0 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x1, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 UniataAhciInit: AHCI Base: 0xf77d9000 MemIo 1 Proc 0 AHCI_0x0 (0xf77d9000) = 0xc8241f80 AHCI_0x4 (0xf77d9004) = 0x80000000 AHCI_0x8 (0xf77d9008) = 0x0 AHCI_0xc (0xf77d900c) = 0x1 AHCI_0x10 (0xf77d9010) = 0x10100 get GHC disable intr, GHC 0x80000000 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xc8241f80 AHCI 64bit AHCI 31 CMD slots AHCI legasy SATA AHCI PI 0x1 AHCI PI mask 0x1 masked AHCI PI 0x1 SATA Gen 2 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 1, 1 luns Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 AtaReq 0xb267f000: cmd aligned b267f080, d=20 ahci_cmd_ptr 0xb267f080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b267d000 AtapiDmaAlloc: CLP BASE 1k-aligned b267d000 AtapiVirtToPhysAddr_: b267d000 -> 00000000:04f7d000 AtapiDmaAlloc: CLP Phys BASE 4f7d000 imp: 0x1 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 4f7d000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 4f7d400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x130 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x0 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 simplexOnly = 0 (2)!MasterDev update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 9, Level2 0, Vector 9, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x1, channel 0x0 de 0xb24167ec, Channel 0x0 chan = 0xb2415b30 AtapiSetupLunPtrs for channel 0 of 1, 1 luns Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 AtaReq 0xb267f000: cmd aligned b267f080, d=20 ahci_cmd_ptr 0xb267f080 AtapiReadChipConfig: devExt 0xb24167ec AtapiReadChipConfig: dev 0x1, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x48 MaxTransferMode (overriden): 0x48 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x48 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 No more setup for AHCI channel IDX_IO1 0->0(io) IDX_IO2 10->f77d9120(mem) IDX_BM_IO 14->0(io) IDX_SATA_IO 19->f77d9128(mem) AtapiDmaAlloc: AHCI already initialized b267d000 exit: init spinlock MasterDev=0x0, NumberChannels=0x1, Isr2DevObj=0x0 Init ISR: Unnecessary MasterDev=0x0, NumberChannels=0x1, Isr2DevObj=0x0 final chan[1] InterruptMode: 0, Level 9, Level2 0, Vector 9, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 UniataAhciInit: AHCI Base: 0xf77d9000 MemIo 1 Proc 0 AHCI_0x0 (0xf77d9000) = 0xc8241f80 AHCI_0x4 (0xf77d9004) = 0x80000002 AHCI_0x8 (0xf77d9008) = 0x0 AHCI_0xc (0xf77d900c) = 0x1 AHCI_0x10 (0xf77d9010) = 0x10100 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xc8241f80 AHCI 64bit AHCI 31 CMD slots AHCI legasy SATA AHCI PI 0x1 AHCI PI mask 0x1 masked AHCI PI 0x1 SATA Gen 2 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 1, 1 luns Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 AtaReq 0xb267f000: cmd aligned b267f080, d=20 ahci_cmd_ptr 0xb267f080 AtapiDmaAlloc: AHCI already initialized b267d000 imp: 0x1 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 4f7d000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 4f7d400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x130 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x0 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 0 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=ffffffff tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xf784cf90, CDB 0xf784cfc0, AtaReq 0xb2404000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf784cf90 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784cc78 ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784cf90 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b2415b30, f784cf90) AtapiStartIo: UniataRemoveRequest(b2415b30, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2415b30, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf784cf90 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf784cf90 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f784cf90) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request ScsiPortInitialize Status 0x0 Parameter IgnoreIsa Parameter IgnoreIsa = 0x0 ATAPI IDE: Look for ISA Controllers AtapiFindController: assume max PIO4 allocate 2 Luns for 1 channels AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb2403568 Lun 0x0 Lun ptr 0xb267a008 Lun 0x1 Lun ptr 0xb267a310 AtapiReadChipConfig: devExt 0xb2403cec AtapiReadChipConfig: dev 0xffffffff, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0xc Parameter MaxTransferMode Parameter MaxTransferMode = 0xc MaxTransferMode (overriden): 0xc Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x0 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x0 VendorID/DeviceID/Rev 0x0/0x0/0x0 Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 AtapiFindController: AtdiskPrimaryClaimed Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 AtapiFindController: AtdiskSecondaryClaimed Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 BaseIoAddress1=1e8 BaseIoAddress2=3ee AltStatus (0xff) Reg_0x1 (0x1e9) = 0xff Reg_0x2 (0x1ea) = 0xff Reg_0x3 (0x1eb) = 0xff Reg_0x4 (0x1ec) = 0xff Reg_0x5 (0x1ed) = 0xff Reg_0x6 (0x1ee) = 0xff Reg_0x7 (0x1ef) = 0xff BM_0x0 (0x0) = 0xa0 BM_0x1 (0x0) = 0xa0 BM_0x2 (0x0) = 0xa0 BM_0x3 (0x0) = 0xa0 AtapiFindController: Identifier read back from Master (0xff) AtapiFindController: Identifier read back from Slave (0xff) Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 BaseIoAddress1=168 BaseIoAddress2=36e AltStatus (0xff) Reg_0x1 (0x169) = 0xff Reg_0x2 (0x16a) = 0xff Reg_0x3 (0x16b) = 0xff Reg_0x4 (0x16c) = 0xff Reg_0x5 (0x16d) = 0xff Reg_0x6 (0x16e) = 0xff Reg_0x7 (0x16f) = 0xff BM_0x0 (0x0) = 0xa0 BM_0x1 (0x0) = 0xa0 BM_0x2 (0x0) = 0xa0 BM_0x3 (0x0) = 0xa0 AtapiFindController: Identifier read back from Master (0xff) AtapiFindController: Identifier read back from Slave (0xff) AtapiFindController: return SP_RETURN_NOT_FOUND ScsiPortInitialize Status 0xc00000c0 Parameter IgnoreMca Parameter IgnoreMca = 0x0 ATAPI IDE: Look for MCA Controllers ScsiPortInitialize Status 0xc00000c0 Leave UNIATA MiniPort DriverEntry with status 0x0 (../../ntoskrnl/io/iomgr/driver.c:1630) '\Driver\BUSLOGIC' initialization failed, status (0xc00000c0) (../../ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\BUSLOGIC' TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d360, CDB 0xf784d390, AtaReq 0xb2417000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf784d360 TopLevel (3), AtaReq 0xb2417000 Try ATAPI send 25 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 25 (Cdb f784d390) assume IN AtapiSendCommand: use_dma=0, Cmd 25 AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f784d390 Command 0x25 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x58) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiStartIo: next Srb f784d360 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x58 base status 0x58 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x58) AtapiInterrupt: iReason 2 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 2 AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: get R wordCount 0x4 IdeIntr: Read 0x4 words IdeIntr: PIO Read AtaReq->DataBuffer 0xf77d8510, srb->DataBuffer 0xf77d8510 status re-check 0x50 AtapiInterrupt: all transferred, AtaReq->WordsLeft == 0 AtapiInterrupt: early complete ? status 50 AtapiInterrupt: CompleteRequest, srbstatus 1 AtapiInterrupt: PIO completion AtapiInterrupt: PIO completion, wait BUSY IdeIntr: ATAPI Read AtaReq->DataBuffer 0xf77d8518, srb->DataBuffer 0xf77d8510, len 0x8 Transfered 8, full size 8 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xf784d360, status 1 AtapiInterrupt: RequestComplete, srb 0xf784d360 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x50 base status 0x50 Unexpected interrupt. OurInterrupt = 2 AtapiInterrupt(base): Catch unexpected AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d364, CDB 0xf784d394, AtaReq 0xb2417000, SCmd 0xbd UniataNeedQueueing: TopLevel, qd=0 Send to device bd TopLevel (2), srb 0xf784d364 TopLevel (3), AtaReq 0xb2417000 Try ATAPI send bd AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD bd (Cdb f784d394) assume IN AtapiSendCommand: use_dma=0, Cmd bd AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f784d394 Command 0xbd to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x80) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiStartIo: next Srb f784d364 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x58 base status 0x58 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x58) AtapiInterrupt: iReason 2 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 2 AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: get R wordCount 0x4 IdeIntr: Read 0x4 words IdeIntr: PIO Read AtaReq->DataBuffer 0xf77d8510, srb->DataBuffer 0xf77d8510 status re-check 0x50 AtapiInterrupt: all transferred, AtaReq->WordsLeft == 0 AtapiInterrupt: early complete ? status 50 AtapiInterrupt: CompleteRequest, srbstatus 1 AtapiInterrupt: PIO completion AtapiInterrupt: PIO completion, wait BUSY IdeIntr: ATAPI Read AtaReq->DataBuffer 0xf77d8518, srb->DataBuffer 0xf77d8510, len 0x8 Transfered 8, full size 8 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xf784d364, status 1 AtapiInterrupt: RequestComplete, srb 0xf784d364 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x50 base status 0x50 Unexpected interrupt. OurInterrupt = 2 AtapiInterrupt(base): Catch unexpected AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d3ec, CDB 0xf784d41c, AtaReq 0xb2417000, SCmd 0x1a UniataNeedQueueing: TopLevel, qd=0 Send to device 1a TopLevel (2), srb 0xf784d3ec TopLevel (3), AtaReq 0xb2417000 Try ATAPI send 1a AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 1a (Cdb f784d41c) assume IN AtapiSendCommand: use_dma=0, Cmd 1a AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f784d41c Command 0x1a to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x41) AtapiSendCommand: Error on cmd: (0x41) AtapiSendCommand: iReason 3 MapError: Error register is 0x50 ATAPI: Illegal request AtapiStartIo: Srb 0xf784d3ec complete with status 0x4 AtapiStartIo: AtapiDmaDBSync(b2682008, f784d3ec) AtapiStartIo: UniataRemoveRequest(b2682008, f784d3ec) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2682008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x41 base status 0x41 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xb267a618, CDB 0xb267a648, AtaReq 0xb2417000, SCmd 0x3 UniataNeedQueueing: TopLevel, qd=0 Send to device 3 TopLevel (2), srb 0xb267a618 TopLevel (3), AtaReq 0xb2417000 Try ATAPI send 3 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 3 (Cdb b267a648) assume IN AtapiSendCommand: SCSIOP_REQUEST_SENSE, no DMA setup AtapiSendCommand: use_dma=0, Cmd 3 AtapiSendCommand: SCSIOP_REQUEST_SENSE -> no dma setup (2) AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb b267a648 Command 0x3 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x41 continue with SCSIOP_REQUEST_SENSE AtapiSendCommand: Entry Status (0x41) AtapiSendCommand: Poll for int. to send packet. Status (0x41) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x80) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiStartIo: next Srb b267a618 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 3) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x58 base status 0x58 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x58) AtapiInterrupt: iReason 2 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 2 AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: get R wordCount 0x9 IdeIntr: Read 0x9 words IdeIntr: PIO Read AtaReq->DataBuffer 0xf77d7540, srb->DataBuffer 0xf77d7540 f0 00 05 00 00 00 00 0a 00 00 00 00 20 00 00 00 00 00 status re-check 0x50 AtapiInterrupt: all transferred, AtaReq->WordsLeft == 0 AtapiInterrupt: early complete ? status 50 AtapiInterrupt: CompleteRequest, srbstatus 1 AtapiInterrupt: PIO completion AtapiInterrupt: PIO completion, wait BUSY IdeIntr: ATAPI Read AtaReq->DataBuffer 0xf77d7552, srb->DataBuffer 0xf77d7540, len 0x12 Transfered 12, full size 12 AtapiInterrupt: RequestComplete AtapiInterrupt: remove srb 0xb267a618, status 1 AtapiInterrupt: RequestComplete, srb 0xb267a618 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x50 base status 0x50 Unexpected interrupt. OurInterrupt = 2 AtapiInterrupt(base): Catch unexpected AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d3ec, CDB 0xf784d41c, AtaReq 0xb2417000, SCmd 0x5a UniataNeedQueueing: TopLevel, qd=0 Send to device 5a TopLevel (2), srb 0xf784d3ec TopLevel (3), AtaReq 0xb2417000 Try ATAPI send 5a AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 5a (Cdb f784d41c) assume IN AtapiSendCommand: use_dma=0, Cmd 5a AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f784d41c Command 0x5a to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x90) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiStartIo: next Srb f784d3ec AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x58 base status 0x58 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x58) AtapiInterrupt: iReason 2 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 2 AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: get R wordCount 0x8 AtapiInterrupt: 12 words requested; 8 words xferred IdeIntr: Read 0x8 words IdeIntr: PIO Read AtaReq->DataBuffer 0xf77d8c48, srb->DataBuffer 0xf77d8c48 status re-check 0x50 AtapiInterrupt: early complete + underrun ? status 50 AtapiInterrupt: CompleteRequest, srbstatus 1 WordsLeft 0x4 -> SRB_STATUS_DATA_OVERRUN AtapiInterrupt: PIO completion AtapiInterrupt: PIO completion, wait BUSY IdeIntr: ATAPI Read AtaReq->DataBuffer 0xf77d8c58, srb->DataBuffer 0xf77d8c48, len 0x18 AtapiInterrupt: Check for underflow, AtaReq->WordsLeft 4 AtapiInterrupt: RequestComplete AtapiInterrupt: remove srb 0xf784d3ec, status 12 AtapiInterrupt: RequestComplete, srb 0xf784d3ec AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x50 base status 0x50 Unexpected interrupt. OurInterrupt = 2 AtapiInterrupt(base): Catch unexpected AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d3ec, CDB 0xf784d41c, AtaReq 0xb2417000, SCmd 0xbe UniataNeedQueueing: TopLevel, qd=0 Send to device be TopLevel (2), srb 0xf784d3ec TopLevel (3), AtaReq 0xb2417000 Try ATAPI send be AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD be (Cdb f784d41c) assume 0-transfer AtapiSendCommand: zero transfer, no DMA setup AtapiSendCommand: use_dma=0, Cmd be AtapiSendCommand: zero transfer AtapiSendCommand: AtapiDmaReinit() to PIO AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device 0 AtapiSendCommand: use_dma=0 AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f784d41c Command 0xbe to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 AtapiSendCommand: Entry Status (0x50) AtapiSendCommand: Poll for int. to send packet. Status (0x50) AtapiSendCommand: status (0x58) AtapiSendCommand: cmd status (0x40) AtapiSendCommand: ExpectingInterrupt (0x1) AtapiSendCommand: return SRB_STATUS_PENDING (3) AtapiStartIo: next Srb f784d3ec AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x1, lch 0x0 DmaTransfer = FALSE DMA status 0x4 perform generic check clear unexpected DMA intr AtapiDmaDone: dev -1 getting status... IDE status 0x40 base status 0x40 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:1, irql 0xc, c 0 dev_type ATAPI OldReqState = 42 continue service interrupt AtapiInterrupt: ATAPI Entered with status (0x40) AtapiInterrupt: iReason 3 AtapiInterrupt: ATAPI branch AtapiInterrupt: iReason 3 AtapiInterrupt: i-reason=3, status=0x40 AtapiInterrupt: interruptReason = CompleteRequest AtapiInterrupt: CompleteRequest, was PIO AtapiInterrupt: wordCount 0x0, WordsTransfered 0x0 AtapiInterrupt: CompleteRequest, srbstatus 1 AtapiInterrupt: PIO completion AtapiInterrupt: PIO completion, wait BUSY IdeIntr: ATAPI Read AtaReq->DataBuffer 0x0, srb->DataBuffer 0x0, len 0x0 Transfered 0, full size 0 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xf784d3ec, status 1 AtapiInterrupt: RequestComplete, srb 0xf784d3ec AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d29c, CDB 0xf784d2cc, AtaReq 0xb2684000, SCmd 0x1a UniataNeedQueueing: TopLevel, qd=0 Send to device 1a TopLevel (2), srb 0xf784d29c TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784d010 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_MODE_SENSE PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784d29c complete with status 0x6 AtapiStartIo: AtapiDmaDBSync(b246b008, f784d29c) AtapiStartIo: UniataRemoveRequest(b246b008, f784d29c) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b246b008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d29c, CDB 0xf784d2cc, AtaReq 0xb2684000, SCmd 0x1a UniataNeedQueueing: TopLevel, qd=0 Send to device 1a TopLevel (2), srb 0xf784d29c TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784d010 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_MODE_SENSE PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784d29c complete with status 0x6 AtapiStartIo: AtapiDmaDBSync(b246b008, f784d29c) AtapiStartIo: UniataRemoveRequest(b246b008, f784d29c) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b246b008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784d2c0, CDB 0xf784d2f0, AtaReq 0xb2684000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf784d2c0 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784d028 ** Ide: Command AtaReq 0xb2684000 ** --- ** ** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x0:0x0:0x0 ** IDE disk 0x0 - #sectors 0x3f, #heads 0x10, #cylinders 0x5145 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784d2c0 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b246b008, f784d2c0) AtapiStartIo: UniataRemoveRequest(b246b008, f784d2c0) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b246b008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xb267ab00, CDB 0xb267ab30, AtaReq 0xb2684000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267ab00 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784cef8 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtapiDmaSetup: mode 0x45, data f77d8000, count 200, lCh 0, dev 0 get Phys(PRD=b2684060) AtapiVirtToPhysAddr_: b2684060 -> 00000000:04f84060 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04d02000 set TERM AtapiDmaSetup: OK IdeReadWrite: Lba 0x0, Count 0x1(0x0) AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xc8, lba 0x0 count 0x1 feature 0x0 Status 0x0 AtapiDmaStart: read on 0x0:0x0 IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267ab00 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 1) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x0, lch 0x0 DmaTransfer = TRUE perform generic check getting status... IDE status 0x50 base status 0x50 AtapiDmaDone: dev -1 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:0, irql 0xd, c 0 DmaTransfer = TRUE dev_type IDE OldReqState = 40 AtapiInterrupt: Entered with status (0x50) AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: CompleteRequest, srbstatus 1 Transfered 200, full size 200 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xb267ab00, status 1 AtapiInterrupt: RequestComplete, srb 0xb267ab00 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xb267ab00, CDB 0xb267ab30, AtaReq 0xb2684000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267ab00 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784ce08 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtapiDmaSetup: mode 0x45, data f77d8000, count 200, lCh 0, dev 0 get Phys(PRD=b2684060) AtapiVirtToPhysAddr_: b2684060 -> 00000000:04f84060 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM AtapiDmaSetup: OK IdeReadWrite: Lba 0x0, Count 0x1(0x0) AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xc8, lba 0x0 count 0x1 feature 0x0 Status 0x0 AtapiDmaStart: read on 0x0:0x0 IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267ab00 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x0, lch 0x0 DmaTransfer = TRUE perform generic check getting status... IDE status 0x50 base status 0x50 AtapiDmaDone: dev -1 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:0, irql 0xd, c 0 DmaTransfer = TRUE dev_type IDE OldReqState = 40 AtapiInterrupt: Entered with status (0x50) AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: CompleteRequest, srbstatus 1 Transfered 200, full size 200 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xb267ab00, status 1 AtapiInterrupt: RequestComplete, srb 0xb267ab00 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xf784cf40, CDB 0xf784cf70, AtaReq 0xb2684000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf784cf40 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784cca8 ** Ide: Command AtaReq 0xb2684000 ** --- ** ** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x0:0x0:0x0 ** IDE disk 0x0 - #sectors 0x3f, #heads 0x10, #cylinders 0x5145 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784cf40 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b246b008, f784cf40) AtapiStartIo: UniataRemoveRequest(b246b008, f784cf40) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b246b008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xb267ab00, CDB 0xb267ab30, AtaReq 0xb2684000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267ab00 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784ce70 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtapiDmaSetup: mode 0x45, data f77d8e00, count 200, lCh 0, dev 0 get Phys(PRD=b2684060) AtapiVirtToPhysAddr_: b2684060 -> 00000000:04f84060 get Phys(data[0]=f77d8e00) AtapiVirtToPhysAddr_: f77d8e00 -> 00000000:04d02e00 set TERM AtapiDmaSetup: OK IdeReadWrite: Lba 0x0, Count 0x1(0x0) AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xc8, lba 0x0 count 0x1 feature 0x0 Status 0x0 AtapiDmaStart: read on 0x0:0x0 IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267ab00 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x0, lch 0x0 DmaTransfer = TRUE perform generic check getting status... IDE status 0x50 base status 0x50 AtapiDmaDone: dev -1 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:0, irql 0xd, c 0 DmaTransfer = TRUE dev_type IDE OldReqState = 40 AtapiInterrupt: Entered with status (0x50) AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: CompleteRequest, srbstatus 1 Transfered 200, full size 200 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xb267ab00, status 1 AtapiInterrupt: RequestComplete, srb 0xb267ab00 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x269e8086/0x0 SRB 0xb267ab00, CDB 0xb267ab30, AtaReq 0xb2684000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267ab00 TopLevel (3), AtaReq 0xb2684000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784ce80 ** Ide: Command AtaReq 0xb2684000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtapiDmaSetup: mode 0x45, data f77d8000, count 200, lCh 0, dev 0 get Phys(PRD=b2684060) AtapiVirtToPhysAddr_: b2684060 -> 00000000:04f84060 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM AtapiDmaSetup: OK IdeReadWrite: Lba 0x0, Count 0x1(0x0) AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0xc8, lba 0x0 count 0x1 feature 0x0 Status 0x0 AtapiDmaStart: read on 0x0:0x0 IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267ab00 AtapiStartIo: query PORT for next request Intr: VendorID+DeviceID/Rev 0x269e8086/0x0 (ex 2) AtapiInterrupt(base): cntrlr 0x0 chan 0x0 AtapiInterrupt(base): try lock AtapiInterrupt(base): locked AtapiCheckInterrupt__: cntrlr 0x0:0x0, lch 0x0 DmaTransfer = TRUE perform generic check getting status... IDE status 0x50 base status 0x50 AtapiDmaDone: dev -1 AtapiCheckInterrupt__: exit with TRUE AtapiInterrupt: cntrlr 0x0:0, irql 0xd, c 0 DmaTransfer = TRUE dev_type IDE OldReqState = 40 AtapiInterrupt: Entered with status (0x50) AtapiInterrupt: i-reason=2, status=0x58 AtapiInterrupt: CompleteRequest, srbstatus 1 Transfered 200, full size 200 AtapiInterrupt: RequestComplete AtapiInterrupt: set AutoSense AtapiInterrupt: remove srb 0xb267ab00, status 1 AtapiInterrupt: RequestComplete, srb 0xb267ab00 AtapiInterrupt: NextRequest, srb=0x0 AtapiInterrupt: ReturnEnableIntr AtapiInterrupt: exiting, UseDpc=1, NoStartIo=1 AtapiInterrupt(base): return status TRUE AtapiInterrupt(base): exit with status 0x1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xf784d29c, CDB 0xf784d2cc, AtaReq 0xb2404000, SCmd 0x1a UniataNeedQueueing: TopLevel, qd=0 Send to device 1a TopLevel (2), srb 0xf784d29c TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784d010 ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_MODE_SENSE PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784d29c complete with status 0x6 AtapiStartIo: AtapiDmaDBSync(b2415b30, f784d29c) AtapiStartIo: UniataRemoveRequest(b2415b30, f784d29c) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2415b30, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xf784d29c, CDB 0xf784d2cc, AtaReq 0xb2404000, SCmd 0x1a UniataNeedQueueing: TopLevel, qd=0 Send to device 1a TopLevel (2), srb 0xf784d29c TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784d010 ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_MODE_SENSE PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784d29c complete with status 0x6 AtapiStartIo: AtapiDmaDBSync(b2415b30, f784d29c) AtapiStartIo: UniataRemoveRequest(b2415b30, f784d29c) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2415b30, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xf784d2c0, CDB 0xf784d2f0, AtaReq 0xb2404000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf784d2c0 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784d028 ** Ide: Command AtaReq 0xb2404000 ** --- ** ** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x0:0x0:0x0 ** IDE disk 0x0 - #sectors 0x3f, #heads 0x10, #cylinders 0x5145 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784d2c0 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b2415b30, f784d2c0) AtapiStartIo: UniataRemoveRequest(b2415b30, f784d2c0) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2415b30, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784cef8 ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8aec AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f79000 set TERM ph data[0]=0:4f79000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8aec AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8000, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8000) AtapiVirtToPhysAddr_: f77d8000 -> 00000000:04f78000 set TERM ph data[0]=0:4f78000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xf784cf40, CDB 0xf784cf70, AtaReq 0xb2404000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf784cf40 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** ** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x0:0x0:0x0 ** IDE disk 0x0 - #sectors 0x3f, #heads 0x10, #cylinders 0x5145 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf784cf40 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b2415b30, f784cf40) AtapiStartIo: UniataRemoveRequest(b2415b30, f784cf40) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b2415b30, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf784ce70 ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8aec AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 AtapiResetController: Reset channel 0 CompleteType 0x1, Luns 1, chan 0xb2415b30, sptr 0x809d8ae4 AtapiResetController: pending SRB 0xb267aab8, chan 0xb2415b30 senseBuffer 0xb2405000, chan 0xb2415b30 AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb2415b30 AHCI path imp: 0x1 & 0x1 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0xfd4000ff AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x50 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 0 Chan 0xb2415b30 Lun 0x0 Lun ptr 0xb2415008 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x8086/0x2829/0x2 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x71 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 171 TFD 0x171 TFD 0x171 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x1 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x10004016 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x171 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 1 WriteChannelPort4 1 => ch0[10] SError 0x0, IS 0x1 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] WriteChannelPort4 f900003f => ch0[14] UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 170 TFD 0x170 34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb2416830, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b2416830, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b267f080) AtapiVirtToPhysAddr_: b267f080 -> 00000000:04f7f080 get Phys(data[0]=b2416830) AtapiVirtToPhysAddr_: b2416830 -> 00000000:04d16830 set TERM ph data[0]=0:4d16830 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x1, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 ReadChannelPort4 ch0[34] = 0 WriteChannelPort4 0 => ch0[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: BVXOH RADDSI K FW: .1 0 S/N: BV177ffc7ee-cd8622 a Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 0 SATA support: 0, CAPs 0x104 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0, cur 0 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 0 CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x5145 NumOfSectors 0x13fffb0 SupportLba flag 0x1 MajorRevision 0x7e UserAddressableSectors 0x1400000 LBA mode LBA48 cylinders 0x5145 NativeNumOfSectors 0x13fffb0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 High-order bytes == Low-order bytes !!! AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 High-order bytes == Low-order bytes !!! (2) Use IDE_COMMAND_READ_NATIVE_SIZE UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x0 requested LunExt->GeomType=2 tmp_cylinders = 0x5145 Geometry: C 0x5145 (0x5145) Geometry: H 0x10 (0x10) Geometry: S 0x3f (0x3f) InitBadBlocks local LunExt 0xb2415008 S/N:VBOX_HARDDISK___________________________-VB71f7cfe7-edc6822a_ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x0) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 40000000 CI 0x1 ReadChannelPort4 ch0[10] = 40000000 IS 0x40000000 WriteChannelPort4 40000000 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 441 TFD 0x441 ERROR 0x4 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 1 Incomplete command, CI 0x1, ACT 0x0 FIS status 0x41, error 0x4 AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x1 AHCI0_0x3c (0xf77d913c) = 0x0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 1000c017 WriteChannelPort4 1000c016 => ch0[18] ReadChannelPort4 ch0[18] = 10004016 final CMD 0x10004016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004006 => ch0[18] ReadChannelPort4 ch0[18] = 10000006 final CMD 0x10000006 UniataAhciCLO: lChan 0 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 10000006 CMD 0x10000006 WriteChannelPort4 10000016 => ch0[18] UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 10004016 CMD 0x10004016 WriteChannelPort4 10004017 => ch0[18] AHCI port 0 Base: 0xf77d9100 MemIo 1 Proc 0 AHCI0_0x0 (0xf77d9100) = 0x4f7d000 AHCI0_0x4 (0xf77d9104) = 0x0 AHCI0_0x8 (0xf77d9108) = 0x4f7d400 AHCI0_0xc (0xf77d910c) = 0x0 AHCI0_0x10 (0xf77d9110) = 0x0 AHCI0_0x14 (0xf77d9114) = 0x0 AHCI0_0x18 (0xf77d9118) = 0x1000c017 AHCI0_0x1c (0xf77d911c) = 0x0 AHCI0_0x20 (0xf77d9120) = 0x441 AHCI0_0x24 (0xf77d9124) = 0x101 AHCI0_0x28 (0xf77d9128) = 0x123 AHCI0_0x2c (0xf77d912c) = 0x300 AHCI0_0x30 (0xf77d9130) = 0x0 AHCI0_0x34 (0xf77d9134) = 0x0 AHCI0_0x38 (0xf77d9138) = 0x0 AHCI0_0x3c (0xf77d913c) = 0x0 try mode 0x48 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x48 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 IDE_STATUS_ERROR detected on entry, statusByte = 0x41 SATA Generic LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb26972a0, AtaReq 0xb267f000, CMD 0xb267f080 ph 4f7f080 AHCI setup FIS b267f080, ch 0, dev 0 27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 00 00 00 00 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb267f000 AHCI AtaReq CMD 0xb267f080 (ph 0x4f7f080) prd_length 0x0, flags 0x5, base 4f7f080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 1 CI 0x1 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 0 TFD 0x0 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x48 mode imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiResetController(1) AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f simplexOnly 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 VendorID+DeviceID/Rev 0x28298086/0x2 imp: 0x1 & 0x1 SRB 0xb267aab8, CDB 0xb267aae8, AtaReq 0xb2404000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb267aab8 TopLevel (3), AtaReq 0xb2404000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809d8a2c ** Ide: Command AtaReq 0xb2404000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb2404000: cmd aligned b2404080, d=20 ahci_cmd_ptr 0xb2404080 AtapiDmaSetup: mode 0x48, data f77d8008, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b2404080) AtapiVirtToPhysAddr_: b2404080 -> 00000000:04d04080 get Phys(data[0]=f77d8008) AtapiVirtToPhysAddr_: f77d8008 -> 00000000:04f77008 set TERM ph data[0]=0:4f77008 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b2404080, ch 0, dev 0 27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 00 00 00 00 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 0, AtaReq 0xb2404000 AHCI AtaReq CMD 0xb2404080 (ph 0x4d04080) prd_length 0x1, flags 0x5, base 4d04080 ReadChannelPort4 ch0[18] = 1000c017 CMD 0x1000c017 WriteChannelPort4 1 => ch0[38] IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b267aab8 AtapiStartIo: query PORT for next request