=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2015.03.11 02:42:24 =~=~=~=~=~=~=~=~=~=~=~=
(../../ntoskrnl/kd/kdio.c:376) -----------------------------------------------------
(../../ntoskrnl/kd/kdio.c:377) ReactOS 0.4-SVN (Build 20150225-rUNKNOWN)
(../../ntoskrnl/kd/kdio.c:379) 1 System Processor [511 MB Memory]
(../../ntoskrnl/kd/kdio.c:380) Command Line: DEBUG DEBUGPORT=COM1 BAUDRATE=115200 SOS MININT
(../../ntoskrnl/kd/kdio.c:384) ARC Paths: multi(0)disk(0)cdrom(96) \ multi(0)disk(0)cdrom(96) \reactos\
(../../ntoskrnl/ke/i386/cpu.c:494) Supported CPU features : KF_V86_VIS KF_RDTSC KF_CR4 KF_CMOV KF_GLOBAL_PAGE KF_LARGE_PAGE KF_MTRR KF_CMPXCHG8B KF_MMX KF_WORKING_PTE KF_PAT KF_FXSR  KF_XMMI   KF_XMMI64    
(../../ntoskrnl/ke/i386/cpu.c:801) Prefetch Cache: 64 bytes	L2 Cache: 1048576 bytes	L2 Cache Line: 64 bytes	L2 Cache Associativity: 4
(../../ntoskrnl/mm/ARM3/mminit.c:1443) HAL I/O Mapping at FFFE0000 is unsafe
(../../ntoskrnl/ke/i386/cpu.c:1088) No support for SYSENTER detected.
(../../ntoskrnl/mm/mminit.c:260)           0x80000000 - 0x83000000	Boot Loaded Image
(../../ntoskrnl/mm/mminit.c:264)           0xB0000000 - 0xB0381000	PFN Database
(../../ntoskrnl/mm/mminit.c:268)           0xB0381000 - 0xB1349000	ARM3 Non Paged Pool
(../../ntoskrnl/mm/mminit.c:272)           0xB9400000 - 0xBB400000	System View Space
(../../ntoskrnl/mm/mminit.c:276)           0xBB400000 - 0xC0000000	Session Space
(../../ntoskrnl/mm/mminit.c:279)           0xC0000000 - 0xC03FFFFF	Page Tables
(../../ntoskrnl/mm/mminit.c:282)           0xC0300000 - 0xC0300FFF	Page Directories
(../../ntoskrnl/mm/mminit.c:285)           0xC0400000 - 0xC07FFFFF	Hyperspace
(../../ntoskrnl/mm/mminit.c:289)           0xE1000000 - 0xEDC00000	ARM3 Paged Pool
(../../ntoskrnl/mm/mminit.c:292)           0xEDC00000 - 0xF8BA8000	System PTE Space
(../../ntoskrnl/mm/mminit.c:295)           0xF8BA8000 - 0xFFBE0000	Non Paged Pool Expansion PTE Space
(../../ntoskrnl/config/cmcheck.c:25) CmCheckRegistry(0xB10F2008, 2) is UNIMPLEMENTED!
(../../hal/halx86/legacy/bussupp.c:594) Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail!
(../../hal/halx86/legacy/bussupp.c:623) Found parent bus (indicating PCI Bridge). PCI devices may fail!

====== PCI BUS HARDWARE DETECTION =======

00:02.0 VGA compatible controller [0300]: InnoTek Systemberatung GmbH VirtualBox Graphics Adapter [80ee:beef] (rev 00)
	Subsystem: Unknown [0000:0000]
	Flags: bus master, fast devsel, latency 0, IRQ 10
	Memory at e0000000 (32-bit, prefetchable) [size=512M]
	Device is using IRQ 10! ISA Cards using that IRQ may fail!

00:04.0 System peripheral [0880]: InnoTek Systemberatung GmbH VirtualBox Guest Service [80ee:cafe] (rev 00)
	Subsystem: Unknown [0000:0000]
	Flags: bus master, fast devsel, latency 0, IRQ 05
	I/O ports at d000 [size=4K]
	Memory at f0000000 (32-bit, non-prefetchable) [size=256M]
	Memory at f0400000 (32-bit, prefetchable) [size=4M]
	Device is using IRQ 5! ISA Cards using that IRQ may fail!

00:07.0 Secondary bus towards host CPU [0680]: Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] (rev 08)
	Subsystem: Unknown [0000:0000]
	Flags: bus master, medium devsel, latency 0, IRQ 09
	Device is using IRQ 9! ISA Cards using that IRQ may fail!

00:18.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev f2)
	Subsystem: Unknown [0000:0000]
	Flags: bus master, 66MHz, fast devsel, latency 0
	Memory at 00010100 (32-bit, non-prefetchable) [size=256]
	Memory at 0000dfe0 (32-bit, non-prefetchable) [size=256]
	Memory at f04ff050 (32-bit, non-prefetchable) [size=4K]
	Memory at 0000fff0 (32-bit, non-prefetchable) [size=256]

00:19.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev f2)
	Subsystem: Unknown [0000:0000]
	Flags: bus master, 66MHz, fast devsel, latency 0
	Memory at 00020200 (32-bit, non-prefetchable) [size=512]
	Memory at 0000dfe0 (32-bit, non-prefetchable) [size=256]
	Memory at f04ff050 (32-bit, non-prefetchable) [size=4K]
	Memory at 0000fff0 (32-bit, non-prefetchable) [size=256]

00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 02)
	Subsystem: Unknown [8086:7270]
	Flags: bus master, medium devsel, latency 0

00:1f.2 SATA controller [0106]: Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode] [8086:2829] (rev 02)
	Subsystem: Unknown [0000:0000]
	Flags: bus master, fast devsel, latency 0, IRQ 09
	I/O ports at e000 [size=8K]
	I/O ports at e008 [size=8]
	I/O ports at e010 [size=16]
	I/O ports at e018 [size=8]
	I/O ports at e020 [size=32]
	Memory at f0500000 (32-bit, non-prefetchable) [size=1M]
	Device is using IRQ 9! ISA Cards using that IRQ may fail!

====== PCI BUS DETECTION COMPLETE =======

PC Compatible Eisa/Isa HAL Detected
(../../ntoskrnl/io/iomgr/driver.c:1630) '\Driver\SACDRV' initialization failed, status (0xc0000037)
(../../ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\SACDRV'


ATAPI IDE MiniPort Driver (UniATA) v 0.45h
 Parameter PrintLogo
 Parameter PrintLogo = 0x0
UniATA Init: OS should be ReactOS
UniATA Init: OS ver 4.1 (1), 1 CPU(s)
Performance calibration: dt=14995, counter=1700448
InitBadBlocks general
InitBadBlocks returned: 0xc0000034
UniataInitAtaCommands:
 Parameter SkipRaids
 Parameter SkipRaids = 0x1
 Parameter ForceSimplex
 Parameter ForceSimplex = 0x0
 Parameter LogToDisplay
 Parameter LogToDisplay = 0x0
HwInitializationDataSize = 50
set NeedPhysicalAddresses = TRUE
set AtapiAdapterControl() ptr


ATAPI IDE enum supported BusMaster Devices
 Parameter VirtualMachineType
 Parameter VirtualMachineType = 0x0
 Parameter VirtualBox
 Parameter VirtualBox = 0x0
-- BusID: 0x0:0x4:0x0 - VirtualBox Guest Service
-- BusID: 0x0:0x1f:0x2
Storage Class
DevId = 28298086 Class = 0001/0006, ProgIf 01
 Parameter Include
 Parameter Include = 0x0
No force include, check exclude
 Parameter Exclude
 Parameter Exclude = 0x0
Default device
found, pass 0
InterruptPin = 0x1
InterruptLine = 0x9
Enabling Mem/Io spaces and busmastering...
Initial pciData.Command = 0x7
PCI_ENABLE_IO_SPACE
PCI_ENABLE_MEMORY_SPACE
PCI_ENABLE_BUS_MASTER
InterruptLine = 0x9
Final pciData.Command = 0x7
Range 0 = 0xe001
Range 1 = 0xe009
Range 2 = 0xe011
Range 3 = 0xe019
Range 4 = 0xe021
Range 5 = 0xf0500000
count: BMListLen++
-- BusID: 0x0:0x4:0x0 - VirtualBox Guest Service
-- BusID: 0x0:0x1f:0x2
Storage Class
DevId = 28298086 Class = 0001/0006, ProgIf 01
 Parameter Include
 Parameter Include = 0x0
No force include, check exclude
 Parameter Exclude
 Parameter Exclude = 0x0
Default device
found, pass 1
InterruptPin = 0x1
InterruptLine = 0x9
Range 0 = 0xe001
Range 1 = 0xe009
Range 2 = 0xe011
Range 3 = 0xe019
Range 4 = 0xe021
Range 5 = 0xf0500000
found suitable device
-- BusID: 0x0:0x4:0x0 - VirtualBox Guest Service
-- BusID: 0x0:0x1f:0x2
Storage Class
DevId = 28298086 Class = 0001/0006, ProgIf 01
 Parameter Include
 Parameter Include = 0x0
No force include, check exclude
 Parameter Exclude
 Parameter Exclude = 0x0
Default device
found, pass 2
InterruptPin = 0x1
InterruptLine = 0x9
Range 0 = 0xe001
Range 1 = 0xe009
Range 2 = 0xe011
Range 3 = 0xe019
Range 4 = 0xe021
Range 5 = 0xf0500000
found suitable device
Add to BMList, AltInit 1
  BMListLen=1
adjust options for VirtualBox
 Parameter WaitBusyCount
 Parameter WaitBusyCount = 0x4e20
 Parameter WaitBusyDelay
 Parameter WaitBusyDelay = 0x96
 Parameter WaitDrqDelay
 Parameter WaitDrqDelay = 0x64
 Parameter WaitBusyLongCount
 Parameter WaitBusyLongCount = 0x4e20
 Parameter WaitBusyLongDelay
 Parameter WaitBusyLongDelay = 0xfa
 Parameter AtapiSendDisableIntr
 Parameter AtapiSendDisableIntr = 0x0
 Parameter AtapiDmaRawRead
 Parameter AtapiDmaRawRead = 0x0
 Parameter MaxIsrWait
 Parameter MaxIsrWait = 0xc8


ATAPI IDE: Look for legacy ISA-bridged PCI IDE controller (onboard)


ATAPI IDE: BMListLen 1
!BMList[i].MasterDev


ATAPI IDE: Look for PCI IDE controller


ATAPI IDE: i 0, BMListLen 1
 Parameter IgnoreNativePci
 Parameter IgnoreNativePci = 0x0
Try init 8086 2829 
(../../hal/halx86/legacy/bussupp.c:1159) Slot assignment for 5 on bus 0
(../../hal/halx86/legacy/bus/pcibus.c:719) WARNING: PCI Slot Resource Assignment is FOOBAR
UniataFindBusMasterController: Context=0, BMListLen=1
ConfigInfo->Length 8c
bm_offset 0, channel 0 
AdapterInterfaceType=0x5
IoBusNumber=0x0
slotNumber=0x5f
busDataRead
DevId = 28298086 Class = 0001/0006
Storage Class
UniataChipDetect:
HwFlags: 0x0
 Parameter ForceSimplex
 Parameter ForceSimplex = 0x0
i: 0x34
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
i: 0x2a
HwFlags: 0x12000000
 Parameter HwFlagsOverride
 Parameter HwFlagsOverride = 0x12000000
HwFlagsOverride: 0x12000000
 Parameter HwFlagsAdd
 Parameter HwFlagsAdd = 0x0
HwFlagsAdd: 0x0
HwFlags (final): 0x12000000
MaxTransferMode: 0x48
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
MaxTransferMode (overriden): 0x48
  UniataAhciDetect:
 Parameter IgnoreAhci
 Parameter IgnoreAhci = 0x0
  AtapiGetIoRange:
  AtapiGetIoRange: rid 0x5, start 0xf0500000, offs 0x0, len 0x10, mem 0x1
  AtapiGetIoRange: 0xf8797000
MemIo
  AHCI Base: 0xf8797000 MemIo 1 Proc 0
  AHCI_0x0 (0xf8797000) = 0xc8241f81
  AHCI_0x4 (0xf8797004) = 0x80000000
  AHCI_0x8 (0xf8797008) = 0x0
  AHCI_0xc (0xf879700c) = 0x3
  AHCI_0x10 (0xf8797010) = 0x10100
  check AHCI mode, GHC 0x80000000
  AHCI CAP 0xc8241f81, CAP2 0x0
  64bit  NCQ  CCC
  AHCI PI 0x3
 Parameter Exclude
 Parameter Exclude = 0x0
 Parameter Exclude
 Parameter Exclude = 0x0
 Parameter PortMask
 Parameter PortMask = 0x3
Force PortMask 0x3
  CommandSlots 31
  Detected Channels 2 / 2
  Adjusted Channels 2
  AHCI version 0x1.10 controller with 2 ports (mask 0x3) detected
  AHCI SATA Gen 2
  PM not supported -> 1 lun/chan
  AHCI detect status 1
allocate 1 Luns for 2 channels
Intel chip config: 0
  AtapiGetIoRange:
  AtapiGetIoRange: rid 0x4, start 0xe020, offs 0x0, len 0x8, mem 0x0
  AtapiGetIoRange: (2) 0xe020
Intel BM check at e020
BM status: ff
invalid BM status, keep AHCI mode
ForceSimplex = 0
HwFlags = 12000000
 (0)HwFlags = 12000000
 (1)HwFlags = 12000000
 (2)found suitable device
HwFlags = 12000000
 (3)  AHCI registers layout
AtapiReadChipConfig: devExt 0xb10ee4bc
AtapiReadChipConfig: dev 0x0, ph chan -1
 Parameter ForceSimplex
 Parameter ForceSimplex = 0x0
MaxTransferMode (base): 0x48
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
MaxTransferMode (overriden): 0x48
 Parameter Force80pin
 Parameter Force80pin = 0x0
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
MaxTransferMode (overriden): 0x48
 Parameter Force80pin
 Parameter Force80pin = 0x0
 Parameter AtapiDmaZeroTransfer
 Parameter AtapiDmaZeroTransfer = 0x0
 Parameter AtapiDmaControlCmd
 Parameter AtapiDmaControlCmd = 0x0
 Parameter AtapiDmaRawRead
 Parameter AtapiDmaRawRead = 0x0
 Parameter AtapiDmaReadWrite
 Parameter AtapiDmaReadWrite = 0x1
AtapiChipInit: dev 0x0, ph chan -2, c -1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  UniataAhciInit:
  AHCI Base: 0xf8797000 MemIo 1 Proc 0
  AHCI_0x0 (0xf8797000) = 0xc8241f81
  AHCI_0x4 (0xf8797004) = 0x80000000
  AHCI_0x8 (0xf8797008) = 0x0
  AHCI_0xc (0xf879700c) = 0x3
  AHCI_0x10 (0xf8797010) = 0x10100
  get GHC
  disable intr, GHC 0x80000000
  reset AHCI controller, GHC 0x80000000
  AHCI GHC 0x80000000
  AHCI GHC 0x80000000
  AHCI CAP 0xc8241f81
  AHCI 64bit
  AHCI 31 CMD slots
  AHCI legasy SATA
  AHCI PI 0x3
  AHCI PI mask 0x3
  masked AHCI PI 0x3
  SATA Gen 2
  chan 0, offs 0x100
AtapiSetupLunPtrs for channel 0 of 2, 1 luns 
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  AtaReq 0xb1319000: cmd aligned b1319080, d=20
  ahci_cmd_ptr 0xb1319080
AtapiDmaAlloc: AHCI
AtapiDmaAlloc: CLP BASE b10eb000
AtapiDmaAlloc: CLP BASE 1k-aligned b10eb000
AtapiVirtToPhysAddr_: b10eb000 -> 00000000:03d6a000
AtapiDmaAlloc: CLP Phys BASE 3d6a000
imp: 0x3 & 0x1
UniataAhciResume: lChan 0
WriteChannelPort4 0 => ch0[14]
  AHCI CLB setup
WriteChannelPort4 3d6a000 => ch0[0]
WriteChannelPort4 0 => ch0[4]
  AHCI RCV FIS setup
WriteChannelPort4 3d6a400 => ch0[8]
WriteChannelPort4 0 => ch0[c]
WriteChannelPort4 10000006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x130
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x0
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  chan 1, offs 0x180
AtapiSetupLunPtrs for channel 1 of 2, 1 luns 
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  AtaReq 0xb131a000: cmd aligned b131a080, d=20
  ahci_cmd_ptr 0xb131a080
AtapiDmaAlloc: AHCI
AtapiDmaAlloc: CLP BASE b1316000
AtapiDmaAlloc: CLP BASE 1k-aligned b1316000
AtapiVirtToPhysAddr_: b1316000 -> 00000000:03f95000
AtapiDmaAlloc: CLP Phys BASE 3f95000
imp: 0x3 & 0x2
UniataAhciResume: lChan 1
WriteChannelPort4 0 => ch1[14]
  AHCI CLB setup
WriteChannelPort4 3f95000 => ch1[0]
WriteChannelPort4 0 => ch1[4]
  AHCI RCV FIS setup
WriteChannelPort4 3f95400 => ch1[8]
WriteChannelPort4 0 => ch1[c]
WriteChannelPort4 10000006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x130
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x0
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
simplexOnly = 0 (2)!MasterDev
update ConfigInfo->nt4
using AtaReq sz 1000
update ConfigInfo->w2k: 64bit 1
chan[0] InterruptMode: 0, Level 9, Level2 0, Vector 9, Vector2 0
Reconstruct ConfigInfo
set Dma32BitAddresses
BMList[i].channel 0x0, NumberChannels 0x2, channel 0x0
de 0xb10ee4bc, Channel 0x0
chan = 0xb1318008
AtapiSetupLunPtrs for channel 0 of 2, 1 luns 
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  AtaReq 0xb1319000: cmd aligned b1319080, d=20
  ahci_cmd_ptr 0xb1319080
AtapiReadChipConfig: devExt 0xb10ee4bc
AtapiReadChipConfig: dev 0x0, ph chan 0
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
MaxTransferMode (overriden): 0x48
 Parameter ReorderEnable
 Parameter ReorderEnable = 0x1
 Parameter Force80pin
 Parameter Force80pin = 0x0
 Parameter ReadCacheEnable
 Parameter ReadCacheEnable = 0x1
 Parameter WriteCacheEnable
 Parameter WriteCacheEnable = 0x1
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
 Parameter PreferedTransferMode
 Parameter PreferedTransferMode = 0xffffffff
 Parameter AdvancedPowerMode
 Parameter AdvancedPowerMode = 0x80
 Parameter AcousticMgmt
 Parameter AcousticMgmt = 0x80
 Parameter StandbyTimer
 Parameter StandbyTimer = 0x0
 Parameter ReadOnly
 Parameter ReadOnly = 0x0
 Parameter GeomType
 Parameter GeomType = 0xffffffff
 Parameter Hidden
 Parameter Hidden = 0x0
  No more setup for AHCI channel
IDX_IO1 0->0(io)
IDX_IO2 10->f8797120(mem)
IDX_BM_IO 14->0(io)
IDX_SATA_IO 19->f8797128(mem)
AtapiDmaAlloc: AHCI
  already initialized b10eb000
de 0xb10ee4bc, Channel 0x1
chan = 0xb1318270
AtapiSetupLunPtrs for channel 1 of 2, 1 luns 
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  AtaReq 0xb131a000: cmd aligned b131a080, d=20
  ahci_cmd_ptr 0xb131a080
AtapiReadChipConfig: devExt 0xb10ee4bc
AtapiReadChipConfig: dev 0x0, ph chan 1
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
MaxTransferMode (overriden): 0x48
 Parameter ReorderEnable
 Parameter ReorderEnable = 0x1
 Parameter Force80pin
 Parameter Force80pin = 0x0
 Parameter ReadCacheEnable
 Parameter ReadCacheEnable = 0x1
 Parameter WriteCacheEnable
 Parameter WriteCacheEnable = 0x1
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0x48
 Parameter PreferedTransferMode
 Parameter PreferedTransferMode = 0xffffffff
 Parameter AdvancedPowerMode
 Parameter AdvancedPowerMode = 0x80
 Parameter AcousticMgmt
 Parameter AcousticMgmt = 0x80
 Parameter StandbyTimer
 Parameter StandbyTimer = 0x0
 Parameter ReadOnly
 Parameter ReadOnly = 0x0
 Parameter GeomType
 Parameter GeomType = 0xffffffff
 Parameter Hidden
 Parameter Hidden = 0x0
  No more setup for AHCI channel
IDX_IO1 0->0(io)
IDX_IO2 10->f87971a0(mem)
IDX_BM_IO 14->0(io)
IDX_SATA_IO 19->f87971a8(mem)
AtapiDmaAlloc: AHCI
  already initialized b1316000
exit: init spinlock
MasterDev=0x0, NumberChannels=0x2, Isr2DevObj=0x0
Init ISR:
Multichannel native mode, go...
Create DO
DO name:  len(38, 38), \Device\uniata0_2ch
HalGetInterruptVector
  OrigAdapterInterfaceType=5
  SystemIoBusNumber=0
  BusInterruptLevel=9
  BusInterruptVector=9
isr2_de 0xb10edd30
isr2_vector 0x39
isr2_irql 0x12
isr2_affinity 0x1
IoConnectInterrupt
MasterDev=0x0, NumberChannels=0x2, Isr2DevObj=0xb10edc78
final chan[2] InterruptMode: 0, Level 9, Level2 0, Vector 9, Vector2 0
return SP_RETURN_FOUND
AtapiHwInitialize: (base)
AtapiChipInit: dev 0xffffffff, ph chan -1, c -1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  UniataAhciInit:
  AHCI Base: 0xf8797000 MemIo 1 Proc 0
  AHCI_0x0 (0xf8797000) = 0xc8241f81
  AHCI_0x4 (0xf8797004) = 0x80000002
  AHCI_0x8 (0xf8797008) = 0x0
  AHCI_0xc (0xf879700c) = 0x3
  AHCI_0x10 (0xf8797010) = 0x10100
  get GHC
  disable intr, GHC 0x80000002
  reset AHCI controller, GHC 0x80000000
  AHCI GHC 0x80000000
  AHCI GHC 0x80000000
  AHCI CAP 0xc8241f81
  AHCI 64bit
  AHCI 31 CMD slots
  AHCI legasy SATA
  AHCI PI 0x3
  AHCI PI mask 0x3
  masked AHCI PI 0x3
  SATA Gen 2
  chan 0, offs 0x100
AtapiSetupLunPtrs for channel 0 of 2, 1 luns 
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  AtaReq 0xb1319000: cmd aligned b1319080, d=20
  ahci_cmd_ptr 0xb1319080
AtapiDmaAlloc: AHCI
  already initialized b10eb000
imp: 0x3 & 0x1
UniataAhciResume: lChan 0
WriteChannelPort4 0 => ch0[14]
  AHCI CLB setup
WriteChannelPort4 3d6a000 => ch0[0]
WriteChannelPort4 0 => ch0[4]
  AHCI RCV FIS setup
WriteChannelPort4 3d6a400 => ch0[8]
WriteChannelPort4 0 => ch0[c]
WriteChannelPort4 10000006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x130
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x0
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  chan 1, offs 0x180
AtapiSetupLunPtrs for channel 1 of 2, 1 luns 
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  AtaReq 0xb131a000: cmd aligned b131a080, d=20
  ahci_cmd_ptr 0xb131a080
AtapiDmaAlloc: AHCI
  already initialized b1316000
imp: 0x3 & 0x2
UniataAhciResume: lChan 1
WriteChannelPort4 0 => ch1[14]
  AHCI CLB setup
WriteChannelPort4 3f95000 => ch1[0]
WriteChannelPort4 0 => ch1[4]
  AHCI RCV FIS setup
WriteChannelPort4 3f95400 => ch1[8]
WriteChannelPort4 0 => ch1[c]
WriteChannelPort4 10000006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x130
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x0
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x0
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 0
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=ffffffff
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x0
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 0
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
AtapiHwInitialize: ATAPI/Changer branch
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiHwInitialize: (base) done
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xf880af90, CDB 0xf880afc0, AtaReq 0xb10da000, SCmd 0x12
UniataNeedQueueing: TopLevel, qd=0
Send to device 12
TopLevel (2), srb 0xf880af90
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0xf880ac78
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x0:0x0:0x0
IdeSendCommand: SCSIOP_INQUIRY ok
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
RelativeAddressing
IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE
AtapiStartIo: Srb 0xf880af90 complete with status 0x1
AtapiStartIo: AtapiDmaDBSync(b1318008, f880af90)
AtapiStartIo: UniataRemoveRequest(b1318008, f880af90)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan b1318008, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
AtapiStartIo: SRB rejected
SRB_STATUS_SELECTION_TIMEOUT
AtapiStartIo: Srb 0xf880af90 complete with status 0xa
AtapiStartIo: UniataRemoveRequest(0, f880af90)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan 0, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x2
  SRB 0xf880af90, CDB 0xf880afc0, AtaReq 0xb10da000, SCmd 0x12
UniataNeedQueueing: TopLevel, qd=0
Send to device 12
TopLevel (2), srb 0xf880af90
TopLevel (3), AtaReq 0xb10da000
Try ATAPI send 12
AtapiSendCommand: req state 0x10, Action 3
AtapiSendCommand: BuildMechanismStatusSrb()
 MechanismStatusSrb 0xb13182ac
AtapiSendCommand: AtapiSendCommand recursive
AtapiSendCommand: req state 0x20, Action 3
AtapiSendCommand: prepare..., ATAPI CMD bd (Cdb b13182dc)
  assume IN
AtapiSendCommand: force use dma (ahci)
AtapiSendCommand: use dma (ahci)
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data b131828c, count 8, lCh 1, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=b131828c)
AtapiVirtToPhysAddr_: b131828c -> 00000000:03f9728c
  set TERM
  ph data[0]=0:3f9728c (7)
AtapiDmaSetup: OK
AtapiSendCommand: setup AHCI FIS
  AHCI setup FIS b10da080, ch 1, dev 0
27 80 a0 01 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
AtapiSendCommand ahci io flags a5: 
AtapiSendCommand: use_dma=1, Cmd bd
  REQ_FLAG_DMA_OPERATION
AtapiSendCommand: AtapiDmaReinit()
AtapiSendCommand: use_dma=1
  REQ_FLAG_DMA_OPERATION
AtapiSendCommand: CMD_ACTION_EXEC
AtapiSendCommand: Cdb b13182dc Command 0xbd to TargetId 0 lun 0
AtapiSendCommand: Entered with status 0x0
ReadChannelPort4 ch1[38] = 0
AtapiSendCommand: AHCI, begin transaction
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0xa5, base 3d59080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  ATAPI
bd 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

  send CMD 0x1100c017, entries 0x1
WriteChannelPort4 1100c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1100c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
AtapiSendCommand: SRB_STATUS_PENDING (2)
AtapiStartIo: next Srb f880af90
AtapiStartIo: query PORT for next request
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcaec
AtapiResetController: pending SRB 0xb13182ac, chan 0xb1318270
  restore original SRB 0xf880af90
  senseBuffer 0xb10db000, chan 0xb1318270
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318270
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1100c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x50
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 1100c016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
  final CMD 0x11004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x11004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 1100c016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
  final CMD 0x11004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004006 => ch1[18]
ReadChannelPort4 ch1[18] = 11000006
  final CMD 0x11000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 11000006
  CMD 0x11000006
WriteChannelPort4 11000016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1100c017
  CMD 0x1100c017
  send CMD 0x1000c017, entries 0x1
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x2
  SRB 0xf880af90, CDB 0xf880afc0, AtaReq 0xb10da000, SCmd 0x12
UniataNeedQueueing: TopLevel, qd=0
Send to device 12
TopLevel (2), srb 0xf880af90
TopLevel (3), AtaReq 0xb10da000
Try ATAPI send 12
AtapiSendCommand: req state 0x10, Action 3
AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f880afc0)
  assume IN
AtapiSendCommand: force use dma (ahci)
AtapiSendCommand: use dma (ahci)
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796158, count 24, lCh 1, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796158)
AtapiVirtToPhysAddr_: f8796158 -> 00000000:03d6d158
  set TERM
  ph data[0]=0:3d6d158 (23)
AtapiDmaSetup: OK
AtapiSendCommand: setup AHCI FIS
  AHCI setup FIS b10da080, ch 1, dev 0
27 80 a0 01 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
AtapiSendCommand ahci io flags a5: 
AtapiSendCommand: use_dma=1, Cmd 12
  REQ_FLAG_DMA_OPERATION
AtapiSendCommand: AtapiDmaReinit()
AtapiSendCommand: use_dma=1
  REQ_FLAG_DMA_OPERATION
AtapiSendCommand: CMD_ACTION_EXEC
AtapiSendCommand: Cdb f880afc0 Command 0x12 to TargetId 0 lun 0
AtapiSendCommand: Entered with status 0x0
ReadChannelPort4 ch1[38] = 0
AtapiSendCommand: AHCI, begin transaction
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0xa5, base 3d59080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  ATAPI
12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 

  send CMD 0x1100c017, entries 0x1
WriteChannelPort4 1100c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1100c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
AtapiStartIo: next Srb f880af90
AtapiStartIo: query PORT for next request
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcaec
AtapiResetController: pending SRB 0xf880af90, chan 0xb1318270
  senseBuffer 0xb10db000, chan 0xb1318270
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318270
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1100c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x50
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 1100c016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
  final CMD 0x11004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x11004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 1100c016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
  final CMD 0x11004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004006 => ch1[18]
ReadChannelPort4 ch1[18] = 11000006
  final CMD 0x11000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 11000006
  CMD 0x11000006
WriteChannelPort4 11000016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1100c017
  CMD 0x1100c017
  send CMD 0x1000c017, entries 0x1
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x2
  SRB 0xf880af90, CDB 0xf880afc0, AtaReq 0xb10da000, SCmd 0x12
UniataNeedQueueing: TopLevel, qd=0
Send to device 12
TopLevel (2), srb 0xf880af90
TopLevel (3), AtaReq 0xb10da000
Try ATAPI send 12
AtapiSendCommand: req state 0x10, Action 3
AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f880afc0)
  assume IN
AtapiSendCommand: force use dma (ahci)
AtapiSendCommand: use dma (ahci)
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796158, count 24, lCh 1, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796158)
AtapiVirtToPhysAddr_: f8796158 -> 00000000:03d6d158
  set TERM
  ph data[0]=0:3d6d158 (23)
AtapiDmaSetup: OK
AtapiSendCommand: setup AHCI FIS
  AHCI setup FIS b10da080, ch 1, dev 0
27 80 a0 01 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
AtapiSendCommand ahci io flags a5: 
AtapiSendCommand: use_dma=1, Cmd 12
  REQ_FLAG_DMA_OPERATION
AtapiSendCommand: AtapiDmaReinit()
AtapiSendCommand: use_dma=1
  REQ_FLAG_DMA_OPERATION
AtapiSendCommand: CMD_ACTION_EXEC
AtapiSendCommand: Cdb f880afc0 Command 0x12 to TargetId 0 lun 0
AtapiSendCommand: Entered with status 0x0
ReadChannelPort4 ch1[38] = 0
AtapiSendCommand: AHCI, begin transaction
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0xa5, base 3d59080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  ATAPI
12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 

  send CMD 0x1100c017, entries 0x1
WriteChannelPort4 1100c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1100c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
AtapiStartIo: next Srb f880af90
AtapiStartIo: query PORT for next request
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcaec
AtapiResetController: pending SRB 0xf880af90, chan 0xb1318270
  senseBuffer 0xb10db000, chan 0xb1318270
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318270
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1100c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x50
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 1100c016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
  final CMD 0x11004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x11004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1100c017
WriteChannelPort4 1100c016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
  final CMD 0x11004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004006 => ch1[18]
ReadChannelPort4 ch1[18] = 11000006
  final CMD 0x11000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 11000006
  CMD 0x11000006
WriteChannelPort4 11000016 => ch1[18]
ReadChannelPort4 ch1[18] = 11004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 11004016
  CMD 0x11004016
WriteChannelPort4 11004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1100c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1100c017
  CMD 0x1100c017
  send CMD 0x1000c017, entries 0x1
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
AtapiStartIo: Communication port
  INQUIRY
AtapiStartIo: Srb 0xf880af90 complete with status 0x1
AtapiStartIo: UniataRemoveRequest(0, f880af90)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan 0, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x1:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
AtapiStartIo: SRB rejected
SRB_STATUS_SELECTION_TIMEOUT
AtapiStartIo: Srb 0xf880af90 complete with status 0xa
AtapiStartIo: UniataRemoveRequest(0, f880af90)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan 0, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
ScsiPortInitialize Status 0x0
 Parameter IgnoreIsa
 Parameter IgnoreIsa = 0x0


ATAPI IDE: Look for ISA Controllers
AtapiFindController:
  assume max PIO4
allocate 2 Luns for 1 channels
AtapiSetupLunPtrs for channel 0 of 1, 2 luns 
  Chan 0xb10d9568
  Lun 0x0
  Lun ptr 0xb1313008
  Lun 0x1
  Lun ptr 0xb1313310
AtapiReadChipConfig: devExt 0xb10d9cec
AtapiReadChipConfig: dev 0xffffffff, ph chan -1
 Parameter ForceSimplex
 Parameter ForceSimplex = 0x0
MaxTransferMode (base): 0xc
 Parameter MaxTransferMode
 Parameter MaxTransferMode = 0xc
MaxTransferMode (overriden): 0xc
 Parameter Force80pin
 Parameter Force80pin = 0x0
 Parameter AtapiDmaZeroTransfer
 Parameter AtapiDmaZeroTransfer = 0x0
 Parameter AtapiDmaControlCmd
 Parameter AtapiDmaControlCmd = 0x0
 Parameter AtapiDmaRawRead
 Parameter AtapiDmaRawRead = 0x0
 Parameter AtapiDmaReadWrite
 Parameter AtapiDmaReadWrite = 0x1
AtapiChipInit: dev 0xffffffff, ph chan -1, c -1
HwFlags: 0x0
VendorID/DeviceID/Rev 0x0/0x0/0x0
 Parameter PortBase
 Parameter PortBase = 0x0
 Parameter Irq
 Parameter Irq = 0x0
  BaseIoAddress1=1f0
  BaseIoAddress2=3f6
  AltStatus (0xff)
  Reg_0x1 (0x1f1) = 0xff
  Reg_0x2 (0x1f2) = 0xff
  Reg_0x3 (0x1f3) = 0xff
  Reg_0x4 (0x1f4) = 0xff
  Reg_0x5 (0x1f5) = 0xff
  Reg_0x6 (0x1f6) = 0xff
  Reg_0x7 (0x1f7) = 0xff
  BM_0x0 (0x0) = 0xa0
  BM_0x1 (0x0) = 0xa0
  BM_0x2 (0x0) = 0xa0
  BM_0x3 (0x0) = 0xa0
AtapiFindController: Identifier read back from Master (0xff)
AtapiFindController: Identifier read back from Slave (0xff)
 Parameter PortBase
 Parameter PortBase = 0x0
 Parameter Irq
 Parameter Irq = 0x0
  BaseIoAddress1=170
  BaseIoAddress2=376
  AltStatus (0xff)
  Reg_0x1 (0x171) = 0xff
  Reg_0x2 (0x172) = 0xff
  Reg_0x3 (0x173) = 0xff
  Reg_0x4 (0x174) = 0xff
  Reg_0x5 (0x175) = 0xff
  Reg_0x6 (0x176) = 0xff
  Reg_0x7 (0x177) = 0xff
  BM_0x0 (0x0) = 0xa0
  BM_0x1 (0x0) = 0xa0
  BM_0x2 (0x0) = 0xa0
  BM_0x3 (0x0) = 0xa0
AtapiFindController: Identifier read back from Master (0xff)
AtapiFindController: Identifier read back from Slave (0xff)
 Parameter PortBase
 Parameter PortBase = 0x0
 Parameter Irq
 Parameter Irq = 0x0
  BaseIoAddress1=1e8
  BaseIoAddress2=3ee
  AltStatus (0xff)
  Reg_0x1 (0x1e9) = 0xff
  Reg_0x2 (0x1ea) = 0xff
  Reg_0x3 (0x1eb) = 0xff
  Reg_0x4 (0x1ec) = 0xff
  Reg_0x5 (0x1ed) = 0xff
  Reg_0x6 (0x1ee) = 0xff
  Reg_0x7 (0x1ef) = 0xff
  BM_0x0 (0x0) = 0xa0
  BM_0x1 (0x0) = 0xa0
  BM_0x2 (0x0) = 0xa0
  BM_0x3 (0x0) = 0xa0
AtapiFindController: Identifier read back from Master (0xff)
AtapiFindController: Identifier read back from Slave (0xff)
 Parameter PortBase
 Parameter PortBase = 0x0
 Parameter Irq
 Parameter Irq = 0x0
  BaseIoAddress1=168
  BaseIoAddress2=36e
  AltStatus (0xff)
  Reg_0x1 (0x169) = 0xff
  Reg_0x2 (0x16a) = 0xff
  Reg_0x3 (0x16b) = 0xff
  Reg_0x4 (0x16c) = 0xff
  Reg_0x5 (0x16d) = 0xff
  Reg_0x6 (0x16e) = 0xff
  Reg_0x7 (0x16f) = 0xff
  BM_0x0 (0x0) = 0xa0
  BM_0x1 (0x0) = 0xa0
  BM_0x2 (0x0) = 0xa0
  BM_0x3 (0x0) = 0xa0
AtapiFindController: Identifier read back from Master (0xff)
AtapiFindController: Identifier read back from Slave (0xff)
AtapiFindController: return SP_RETURN_NOT_FOUND
ScsiPortInitialize Status 0xc00000c0
 Parameter IgnoreMca
 Parameter IgnoreMca = 0x0


ATAPI IDE: Look for MCA Controllers
ScsiPortInitialize Status 0xc00000c0


Leave UNIATA MiniPort DriverEntry with status 0x0
(../../ntoskrnl/io/iomgr/driver.c:1630) '\Driver\BUSLOGIC' initialization failed, status (0xc00000c0)
(../../ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\BUSLOGIC'
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xf880b29c, CDB 0xf880b2cc, AtaReq 0xb10da000, SCmd 0x1a
UniataNeedQueueing: TopLevel, qd=0
Send to device 1a
TopLevel (2), srb 0xf880b29c
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0xf880b010
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_MODE_SENSE PATH:LUN:TID = 0x0:0x0:0x0
IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE
AtapiStartIo: Srb 0xf880b29c complete with status 0x6
AtapiStartIo: AtapiDmaDBSync(b1318008, f880b29c)
AtapiStartIo: UniataRemoveRequest(b1318008, f880b29c)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan b1318008, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xf880b29c, CDB 0xf880b2cc, AtaReq 0xb10da000, SCmd 0x1a
UniataNeedQueueing: TopLevel, qd=0
Send to device 1a
TopLevel (2), srb 0xf880b29c
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0xf880b010
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_MODE_SENSE PATH:LUN:TID = 0x0:0x0:0x0
IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE
AtapiStartIo: Srb 0xf880b29c complete with status 0x6
AtapiStartIo: AtapiDmaDBSync(b1318008, f880b29c)
AtapiStartIo: UniataRemoveRequest(b1318008, f880b29c)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan b1318008, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xf880b2c0, CDB 0xf880b2f0, AtaReq 0xb10da000, SCmd 0x25
UniataNeedQueueing: TopLevel, qd=0
Send to device 25
TopLevel (2), srb 0xf880b2c0
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0xf880b028
** Ide: Command AtaReq 0xb10da000
** --- **
** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x0:0x0:0x0
** IDE disk 0x0 - #sectors 0x3f, #heads 0x10, #cylinders 0x5145
IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE
AtapiStartIo: Srb 0xf880b2c0 complete with status 0x1
AtapiStartIo: AtapiDmaDBSync(b1318008, f880b2c0)
AtapiStartIo: UniataRemoveRequest(b1318008, f880b2c0)
AtapiStartIo: ScsiPortNotification
AtapiStartIo: UniataGetCurRequest
AtapiStartIo: chan b1318008, Src 0
AtapiStartIo: next Srb 0
AtapiStartIo: query PORT for next request
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0xf880aef8
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcaec
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
AtapiResetController: deviceExtension->chan[1].DisableIntr 1 -> 1
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
imp: 0x3 & 0x2
AtapiChipInit: dev 0xffffffff, ph chan 1, c 1
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
FindDevices:
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch1[24] = eb140101
  ATAPI at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x2
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
ReadChannelPort4 ch1[34] = 0
WriteChannelPort4 0 => ch1[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 50
  TFD 0x50
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOC -DOR M        
FW:    .1 0
S/N:   BV-1a1b2c3d4        
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
InitBadBlocks local
LunExt 0xb10ed310
S/N:VBOX_CD-ROM_____________________________-VB1-1a2b3c4d________
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: Device is CD/Optical drive.
IssueIdentify: AtapiCmdSize 0x0
IssueIdentify: final Status on exit (0x50)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x1, dev 0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 1/0
AtapiDisableInterrupts_1: 1
WriteChannelPort4 0 => ch1[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x0, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciStatus(1-1):
 hIS 0x0
UniataAhciEndTransaction: lChan 1
ReadChannelPort4 ch1[20] = 0
  TFD 0x0
ReadChannelPort4 ch1[34] = 0
ReadChannelPort4 ch1[38] = 0
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 2
WriteChannelPort4 0 => ch1[14]
Using 0x48 mode
imp: 0x3 & 0x2
AtapiEnableInterrupts_1: 1
WriteChannelPort4 fd4000ff => ch1[14]
AtapiResetController(2)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
TopLevel
** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0
   VendorID+DeviceID/Rev 0x28298086/0x2
imp: 0x3 & 0x1
  SRB 0xb131c2c8, CDB 0xb131c2f8, AtaReq 0xb10da000, SCmd 0x28
UniataNeedQueueing: TopLevel, qd=0
Send to device 28
TopLevel (2), srb 0xb131c2c8
TopLevel (3), AtaReq 0xb10da000
Try IDE send
** Ide: Command: entryway
** Ide: Command:

** Ide: Command &AtaReq 0x809dca2c
** Ide: Command AtaReq 0xb10da000
** --- **
IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x0:0x0:0x0
IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1
IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1
  AtaReq 0xb10da000: cmd aligned b10da080, d=20
  ahci_cmd_ptr 0xb10da080
AtapiDmaSetup: mode 0x48, data f8796000, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b10da080)
AtapiVirtToPhysAddr_: b10da080 -> 00000000:03d59080
  get Phys(data[0]=f8796000)
AtapiVirtToPhysAddr_: f8796000 -> 00000000:03d57000
  set TERM
  ph data[0]=0:3d57000 (1ff)
AtapiDmaSetup: OK
IdeReadWrite: setup AHCI FIS
  AHCI setup FIS b10da080, ch 0, dev 0
27 80 c8 00 00 00 00 e0 00 00 00 00 01 00 00 80 
00 00 00 00 
IdeReadWrite ahci io flags 5: 
AtapiDmaReinit: ahci, nothing to do for HDD
IdeReadWrite: Lba 0x0, Count 0x1(0x0)
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb10da000
  AHCI AtaReq CMD 0xb10da080 (ph 0x3d59080)
  prd_length 0x1, flags 0x5, base 3d59080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
IdeSendCommand: SRB_STATUS_PENDING
IdeSendCommand: REQ_STATE_EXPECTING_INTR
AtapiStartIo: next Srb b131c2c8
AtapiStartIo: query PORT for next request
AtapiResetController(0)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 0
  CompleteType 0x1, Luns 1, chan 0xb1318008, sptr 0x809dcae4
AtapiResetController: pending SRB 0xb131c2c8, chan 0xb1318008
  senseBuffer 0xb10db000, chan 0xb1318008
AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET
chan 0xb1318008
  AHCI path
imp: 0x3 & 0x1
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0xfd4000ff
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x50
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
  process connected devices 0 - 0
  Chan 0xb1318008
  Lun 0x0
  Lun ptr 0xb10ed008
  found some device
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
AtapiResetController: deviceExtension->chan[0].DisableIntr 1 -> 1
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
imp: 0x3 & 0x1
AtapiChipInit: dev 0xffffffff, ph chan 0, c 0
HwFlags: 0x12000000
VendorID/DeviceID/Rev 0x8086/0x2829/0x2
  AHCI single channel init
UniataAhciReset: lChan 0
WriteChannelPort4 0 => ch0[14]
UniataAhciHardReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x71
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 171
  TFD 0x171
  TFD 0x171
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x1
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x10004016
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x171
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
ReadChannelPort4 ch0[24] = 101
  sig: 0x101
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 1
WriteChannelPort4 1 => ch0[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 f900003f => ch0[14]
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0x101
  ATA dev
FindDevices:
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
  max_ldev 1
CheckDevice: Device 0x0
SStatus 123
  AHCI check
ReadChannelPort4 ch0[24] = 101
  AHCI HDD at home
CheckDevice: reset AHCI dev
UniataAhciSoftReset: lChan 0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 1
  CI 0x1
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciSendCommand: lChan 0
WriteChannelPort4 1 => ch0[38]
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch0[10]
UniataAhciWaitReady: lChan 0
ReadChannelPort4 ch0[20] = 170
  TFD 0x170
34 00 00 01 01 00 00 00 00 00 00 00 01 00 00 00 
00 00 00 00 
IssueIdentify: Checking for IDE. Status (0x50)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ec 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 0, dev 0
  get Phys(AHCI_CMD=b1319080)
AtapiVirtToPhysAddr_: b1319080 -> 00000000:03f98080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x1, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x1
ReadChannelPort4 ch0[10] = 0
ReadChannelPort4 ch0[38] = 0
ReadChannelPort4 ch0[34] = 0
WriteChannelPort4 0 => ch0[10]
 AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000
 AHCI: complete mask 0x1
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
IssueIdentify: Status after read words 0x50
Model: BVXOH RADDSI K      
FW:    .1 0
S/N:   BV7c08f69cf-69fd5e f
Pio:   0
APio:  3
SWDMA: 0
MWDMA: 0
UDMA:  40/7f
SATA:  0
SATA support: 0, CAPs 0x104
OrigTransferMode: 48, Active: 48
Accoustic 0, cur 0
AdvPowerMode 0, cur 0
PhysLogSectorSize 0x0, 0x0, offset 0x0
NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0
R-rate 0
CHS 0x3fff:0x10:0x3f
NumOfSectors 0xfbfc10
NumberOfCylinders == 0x3fff
cylinders 0x5145
NumOfSectors 0x13fffb0
SupportLba flag 0x1
MajorRevision 0x7e
UserAddressableSectors 0x1400000
LBA mode
LBA48
cylinders 0x5145
NativeNumOfSectors 0x13fffb0
Use IDE_COMMAND_READ_NATIVE_SIZE48
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
High-order bytes == Low-order bytes !!!
AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0
  (ahci)
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 27 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
High-order bytes == Low-order bytes !!! (2)
Use IDE_COMMAND_READ_NATIVE_SIZE
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xf8, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 f8 00 00 00 00 e0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
NativeNumOfSectors 0x0
requested LunExt->GeomType=2
tmp_cylinders = 0x5145
Geometry: C 0x5145 (0x5145)
Geometry: H 0x10 (0x10)
Geometry: S 0x3f (0x3f)
InitBadBlocks local
LunExt 0xb10ed008
S/N:VBOX_HARDDISK___________________________-VBc7806fc9-f96dfe5f_
IssueIdentify: Device does not interrupt on assertion of DRQ.
IssueIdentify: hard drive.
IssueIdentify: final Status on exit (0x0)
CheckDevice: detected AHCI Device 0x0
CheckDevice: check status: found
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
FindDevices: returning 1 (AHCI)
AtapiHwInitialize: lChannel 0x0, dev 0
AtapiDisableInterrupts_0: 0
WriteChannelPort4 0 => ch0[14]
AtapiHwInitialize: IDE branch
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 c6 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0
  Try Enable Read Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef aa 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Write Cache
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 02 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 50
  TFD 0x50
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
  Try Enable Adv. Power Mgmt
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 05 00 00 00 a0 00 00 00 00 80 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 1
ReadChannelPort4 ch0[10] = 40000000
  CI 0x1
ReadChannelPort4 ch0[10] = 40000000
  IS 0x40000000
WriteChannelPort4 40000000 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 441
  TFD 0x441
  ERROR 0x4
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 1
  Incomplete command, CI 0x1, ACT 0x0
  FIS status 0x41, error 0x4
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x1
  AHCI0_0x3c (0xf879713c) = 0x0
UniataAhciStop: lChan 0
ReadChannelPort4 ch0[18] = 1000c017
WriteChannelPort4 1000c016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch0[18]
ReadChannelPort4 ch0[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 0
UniataAhciStartFR: lChan 0
ReadChannelPort4 ch0[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch0[18]
ReadChannelPort4 ch0[18] = 10004016
UniataAhciStart: lChan 0
ReadChannelPort4 ch0[10] = 0
WriteChannelPort4 0 => ch0[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch0[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
  AHCI port 0 Base: 0xf8797100 MemIo 1 Proc 0
  AHCI0_0x0 (0xf8797100) = 0x3d6a000
  AHCI0_0x4 (0xf8797104) = 0x0
  AHCI0_0x8 (0xf8797108) = 0x3d6a400
  AHCI0_0xc (0xf879710c) = 0x0
  AHCI0_0x10 (0xf8797110) = 0x0
  AHCI0_0x14 (0xf8797114) = 0x0
  AHCI0_0x18 (0xf8797118) = 0x1000c017
  AHCI0_0x1c (0xf879711c) = 0x0
  AHCI0_0x20 (0xf8797120) = 0x441
  AHCI0_0x24 (0xf8797124) = 0x101
  AHCI0_0x28 (0xf8797128) = 0x123
  AHCI0_0x2c (0xf879712c) = 0x300
  AHCI0_0x30 (0xf8797130) = 0x0
  AHCI0_0x34 (0xf8797134) = 0x0
  AHCI0_0x38 (0xf8797138) = 0x0
  AHCI0_0x3c (0xf879713c) = 0x0
  try mode 0x48
AtapiDmaInit__: Set (U)DMA on Device 0
AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA
AtapiDmaInit: LunExt->LimitedTransferMode 0x48
AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA   =>   0x6
IDE_STATUS_ERROR detected on entry, statusByte = 0x41
SATA Generic
LunExt->LimitedTransferMode 48, LunExt->OrigTransferMode 48
AtaSetTransferMode: Set 0x48 on Device 0/0
AtapiDisableInterrupts_0: 1
WriteChannelPort4 0 => ch0[14]
UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 0 [0x0]
  Srb 0xb10ee188, AtaReq 0xb1319000, CMD 0xb1319080 ph 3f98080
  AHCI setup FIS b1319080, ch 0, dev 0
27 80 ef 03 00 00 00 a0 00 00 00 00 46 00 00 80 
00 00 00 00 
ahci_flags 0x5
UniataAhciBeginTransaction: lChan 0, AtaReq 0xb1319000
  AHCI AtaReq CMD 0xb1319080 (ph 0x3f98080)
  prd_length 0x0, flags 0x5, base 3f98080
ReadChannelPort4 ch0[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch0[38]
  Send CMD START
WriteChannelPort4 1000c017 => ch0[18]
ReadChannelPort4 ch0[18] = 1000c017
ReadChannelPort4 ch0[38] = 0
  CI 0x0
ReadChannelPort4 ch0[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch0[10]
UniataAhciStatus(0-0):
 hIS 0x0
UniataAhciEndTransaction: lChan 0
ReadChannelPort4 ch0[20] = 0
  TFD 0x0
ReadChannelPort4 ch0[34] = 0
ReadChannelPort4 ch0[38] = 0
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 2
WriteChannelPort4 0 => ch0[14]
Using 0x48 mode
imp: 0x3 & 0x1
AtapiEnableInterrupts_0: 1
WriteChannelPort4 fd4000ff => ch0[14]
AtapiResetController(1)
AtapiResetController: Reset IDE 0x8086/0x2829 @ 0x5f
simplexOnly 0
AtapiResetController: Reset channel 1
  CompleteType 0x1, Luns 1, chan 0xb1318270, sptr 0x809dcae4
  AHCI path
imp: 0x3 & 0x2
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x0
  AHCI1_0x14 (0xf8797194) = 0xfd4000ff
  AHCI1_0x18 (0xf8797198) = 0x1000c017
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x0
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
AtapiDisableInterrupts_1: 0
WriteChannelPort4 0 => ch1[14]
UniataAhciReset: lChan 1
WriteChannelPort4 0 => ch1[14]
UniataAhciHardReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataSataPhyEnable:
SControl 0x300
UniataSataPhyEnable: retry init 0
  SControl 00000001
UniataSataPhyEnable: retry idle 0
  SControl 00000300
UniataSataConnect:
SATA TransferMode 0x48
UniataSataConnect: OK, ATA status 0x31
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 131
  TFD 0x131
  TFD 0x131
  AHCI port 1 Base: 0xf8797180 MemIo 1 Proc 0
  AHCI1_0x0 (0xf8797180) = 0x3f95000
  AHCI1_0x4 (0xf8797184) = 0x0
  AHCI1_0x8 (0xf8797188) = 0x3f95400
  AHCI1_0xc (0xf879718c) = 0x0
  AHCI1_0x10 (0xf8797190) = 0x1
  AHCI1_0x14 (0xf8797194) = 0x0
  AHCI1_0x18 (0xf8797198) = 0x10004016
  AHCI1_0x1c (0xf879719c) = 0x0
  AHCI1_0x20 (0xf87971a0) = 0x131
  AHCI1_0x24 (0xf87971a4) = 0xeb140101
  AHCI1_0x28 (0xf87971a8) = 0x123
  AHCI1_0x2c (0xf87971ac) = 0x300
  AHCI1_0x30 (0xf87971b0) = 0x0
  AHCI1_0x34 (0xf87971b4) = 0x0
  AHCI1_0x38 (0xf87971b8) = 0x0
  AHCI1_0x3c (0xf87971bc) = 0x0
ReadChannelPort4 ch1[24] = eb140101
  sig: 0xeb140101
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 1
WriteChannelPort4 1 => ch1[10]
    SError 0x0, IS 0x1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 f900003f => ch1[14]
UniataAhciSoftReset: lChan 1
UniataAhciStop: lChan 1
ReadChannelPort4 ch1[18] = 1000c017
WriteChannelPort4 1000c016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
  final CMD 0x10004016
UniataAhciStopFR: lChan 1
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004006 => ch1[18]
ReadChannelPort4 ch1[18] = 10000006
  final CMD 0x10000006
UniataAhciCLO: lChan 1
UniataAhciStartFR: lChan 1
ReadChannelPort4 ch1[18] = 10000006
  CMD 0x10000006
WriteChannelPort4 10000016 => ch1[18]
ReadChannelPort4 ch1[18] = 10004016
UniataAhciStart: lChan 1
ReadChannelPort4 ch1[10] = 0
WriteChannelPort4 0 => ch1[10]
    SError 0x0, IS 0x0
ReadChannelPort4 ch1[18] = 10004016
  CMD 0x10004016
WriteChannelPort4 10004017 => ch1[18]
ReadChannelPort4 ch1[18] = 1000c017
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 1
  CI 0x1
ReadChannelPort4 ch1[10] = 1
  IS 0x1
WriteChannelPort4 1 => ch1[10]
UniataAhciSendCommand: lChan 1
WriteChannelPort4 1 => ch1[38]
ReadChannelPort4 ch1[38] = 1
ReadChannelPort4 ch1[10] = 0
ReadChannelPort4 ch1[38] = 0
  CI 0x0
ReadChannelPort4 ch1[10] = 0
  IS 0x0
WriteChannelPort4 0 => ch1[10]
UniataAhciWaitReady: lChan 1
ReadChannelPort4 ch1[20] = 130
  TFD 0x130
34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 
00 00 00 00 
  signature 0xeb140101
  ATAPI dev
  process connected devices 0 - 0
  Chan 0xb1318270
  Lun 0x0
  Lun ptr 0xb10ed310
  found some device
IssueIdentify: Checking for ATAPI. Status (0x30)
UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb10ee500, len 0x200, WF 0x2 
  length/DEV_BSIZE != bcount
BuildAhciInternalSrb: lChan 1 [0x0]
  Srb 0xb10ee1c8, AtaReq 0xb131a000, CMD 0xb131a080 ph 3f99080
  AHCI setup FIS b131a080, ch 1, dev 0
27 80 a1 00 00 00 00 a0 00 00 00 00 00 00 00 80 
00 00 00 00 
ahci_flags 0x5
  assume IN
AtapiDmaSetup: mode 0x48, data b10ee500, count 200, lCh 1, dev 0
  get Phys(AHCI_CMD=b131a080)
AtapiVirtToPhysAddr_: b131a080 -> 00000000:03f99080
  get Phys(data[0]=b10ee500)
AtapiVirtToPhysAddr_: b10ee500 -> 00000000:03d6d500
  set TERM
  ph data[0]=0:3d6d500 (1ff)
AtapiDmaSetup: OK
UniataAhciBeginTransaction: lChan 1, AtaReq 0xb131a000
  AHCI AtaReq CMD 0xb131a080 (ph 0x3f99080)
  prd_length 0x1, flags 0x5, base 3f99080
ReadChannelPort4 ch1[18] = 1000c017
  CMD 0x1000c017
  Set CI
WriteChannelPort4 1 => ch1[38]
  Send CMD START
WriteChanne