diff -ruN v45h4\chglog.txt v45h9\chglog.txt --- v45h4\chglog.txt Mon Apr 06 17:36:50 2015 +++ v45h9\chglog.txt Wed Sep 23 19:35:10 2015 @@ -899,3 +899,43 @@ !) fixed bug with missing REQ_FLAG_DMA_OPERATION on succefull reinit in AtapiDmaSetup(). This prevented fallback to UDMA2 when higher modes doesn't work fine. + +-- +2015.04.07 - v0.45h5 + +*) minor log updates + +-- +2015.09.22 - v0.45h6 + ++) added BOCHS detection ++) implemented quick device absence detection for BOCHS (0x00 status) +!) unified IORES structure init via UniataInitIoRes() and UniataInitIoResEx() +this affects problem with ReactOS boot under BOCHS (BUG 10176) +e!) IORES->Proc check in IO routines replaced with ASSERT() +also affets ReactOS BUG 10176 +!) fixed bug with missing reinit dma after device reset and initial +detection. +!) added IO size alignment check before 32-bit PIO operations +!) fixed bug with Intel timings (secondary channel) + +-- +2015.09.23 - v0.45h7 + +e) added optimization to avoid unnecessary IO with unsupported/missing +PCI devices on 2nd and 3rd scan passes. + +-- +2015.09.23 - v0.45h8 + ++) sync with ReactOS repository +e) handle PRD and IO-buff double-buffering before sending CMD to device. +Copying is moved from AtapiDmaStar() to AtapiDmaDBPreSync() ++) #pragma pack(1) is used for BusMaster structures in 'bsmaster.h' + +-- +2015.09.23 - v0.45h9 + +!) #pragma pack() is used in all uniata headers to avoid cross-environemnt +ambiguities + diff -ruN v45h4\driver\atapi.h v45h9\driver\atapi.h --- v45h4\driver\atapi.h Sun Feb 22 09:48:12 2015 +++ v45h9\driver\atapi.h Wed Sep 23 02:05:38 2015 @@ -1486,6 +1486,23 @@ IN struct _HW_CHANNEL* chan ); +VOID +UniataInitIoRes( + IN struct _HW_CHANNEL* chan, + IN ULONG idx, + IN ULONG addr, + IN BOOLEAN MemIo, + IN BOOLEAN Proc + ); + +VOID +UniataInitIoResEx( + IN struct _IORES* IoRes, + IN ULONG addr, + IN BOOLEAN MemIo, + IN BOOLEAN Proc + ); + UCHAR DDKFASTAPI UniataIsIdle( diff -ruN v45h4\driver\bm_devs.h v45h9\driver\bm_devs.h --- v45h4\driver\bm_devs.h Tue Feb 24 02:09:50 2015 +++ v45h9\driver\bm_devs.h Wed Sep 23 19:05:02 2015 @@ -31,6 +31,11 @@ --*/ +#ifndef __IDE_BUSMASTER_DEVICES_H__ +#define __IDE_BUSMASTER_DEVICES_H__ + +#pragma pack(push, 8) + #define IDE_MAX_CHAN 16 #define IDE_DEFAULT_MAX_CHAN 2 // Thanks to SATA Port Multipliers: @@ -47,9 +52,6 @@ //#define UniataGetPioTiming(LunExt) ((LunExt->TransferMode <= ATA_PIO0) ? PIO0_TIMING : 0) #define UniataGetPioTiming(LunExt) 0 //ktp -#ifndef __IDE_BUSMASTER_DEVICES_H__ -#define __IDE_BUSMASTER_DEVICES_H__ - /*#ifdef USER_MODE #define PVEN_STR PCSTR #else // USER_MODE @@ -1274,5 +1276,7 @@ (pciData)->ProgIf == PCI_DEV_PROGIF_AHCI_1_0 && \ ((pciData)->u.type0.BaseAddresses[5] & ~0x7)) + +#pragma pack(pop) #endif //__IDE_BUSMASTER_H__ diff -ruN v45h4\driver\bsmaster.h v45h9\driver\bsmaster.h --- v45h4\driver\bsmaster.h Thu Oct 30 08:36:00 2014 +++ v45h9\driver\bsmaster.h Wed Sep 23 19:07:18 2015 @@ -64,6 +64,8 @@ #include "uata_ctl.h" +#pragma pack(push, 8) + #define MAX_RETRIES 6 #define RETRY_UDMA2 1 #define RETRY_WDMA 2 @@ -114,6 +116,8 @@ #define PCI_DEV_PROGIF_AHCI_1_0 0x01 +#pragma pack(push, 1) + /* structure for holding DMA address data */ typedef struct BM_DMA_ENTRY { ULONG base; @@ -836,6 +840,7 @@ IDE_AHCI_CMD cmd; // for single internal commands w/o associated AtaReq } IDE_AHCI_CHANNEL_CTL_BLOCK, *PIDE_AHCI_CHANNEL_CTL_BLOCK; +#pragma pack(pop) #define IsBusMaster(pciData) \ ( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \ @@ -1483,6 +1488,14 @@ PSCSI_REQUEST_BLOCK Srb ); +extern BOOLEAN +NTAPI +AtapiDmaDBPreSync( + IN PVOID HwDeviceExtension, + PHW_CHANNEL chan, + PSCSI_REQUEST_BLOCK Srb + ); + extern VOID NTAPI AtapiDmaStart( @@ -1865,9 +1878,12 @@ #define VM_VBOX 0x02 #define VM_VMWARE 0x03 #define VM_QEMU 0x04 +#define VM_BOCHS 0x05 #define VM_MAX_KNOWN VM_QEMU extern BOOLEAN WinVer_WDM_Model; + +#pragma pack(pop) #endif //__IDE_BUSMASTER_H__ diff -ruN v45h4\driver\Dist\2K\uata_2k.inf v45h9\driver\Dist\2K\uata_2k.inf --- v45h4\driver\Dist\2K\uata_2k.inf Mon Apr 06 17:37:18 2015 +++ v45h9\driver\Dist\2K\uata_2k.inf Wed Sep 23 19:35:40 2015 @@ -6,7 +6,7 @@ ClassGUID={4D36E97B-E325-11CE-BFC1-08002BE10318} Class=SCSIAdapter CatalogFile=uniata.cat -DriverVer=04/06/2015,0.45.8.4 +DriverVer=09/23/2015,0.45.8.9 ; ; Source file information diff -ruN v45h4\driver\Dist\2K\uata_2kh.inf v45h9\driver\Dist\2K\uata_2kh.inf --- v45h4\driver\Dist\2K\uata_2kh.inf Mon Apr 06 17:37:18 2015 +++ v45h9\driver\Dist\2K\uata_2kh.inf Wed Sep 23 19:35:40 2015 @@ -6,7 +6,7 @@ ClassGUID={4D36E97B-E325-11CE-BFC1-08002BE10318} Class=hdc CatalogFile=uniata.cat -DriverVer=04/06/2015,0.45.8.4 +DriverVer=09/23/2015,0.45.8.9 ; ; Source file information diff -ruN v45h4\driver\Dist\2K\uniata_w2k.reg v45h9\driver\Dist\2K\uniata_w2k.reg --- v45h4\driver\Dist\2K\uniata_w2k.reg Mon Apr 06 17:37:18 2015 +++ v45h9\driver\Dist\2K\uniata_w2k.reg Wed Sep 23 19:35:40 2015 @@ -6,7 +6,7 @@ "Start"=dword:00000000 "Tag"=dword:00000019 "Type"=dword:00000001 -"DisplayName"="Universal BusMaster SATA/ATA/ATAPI Driver v0.45.8.4" +"DisplayName"="Universal BusMaster SATA/ATA/ATAPI Driver v0.45.8.9" "ImagePath"=hex(2):53,79,73,74,65,6d,33,32,5c,44,52,49,56,45,52,53,5c,75,6e,69,\ 61,74,61,2e,73,79,73,00 diff -ruN v45h4\driver\Dist\NT4\uata_nt4.inf v45h9\driver\Dist\NT4\uata_nt4.inf --- v45h4\driver\Dist\NT4\uata_nt4.inf Mon Apr 06 17:37:16 2015 +++ v45h9\driver\Dist\NT4\uata_nt4.inf Wed Sep 23 19:35:38 2015 @@ -6,7 +6,7 @@ ClassGUID={4D36E97B-E325-11CE-BFC1-08002BE10318} Class=SCSIAdapter CatalogFile=uniata.cat -DriverVer=04/06/2015,0.45.8.4 +DriverVer=09/23/2015,0.45.8.9 ; ; Source file information Binary files v45h4\driver\Dist\tools\build_inf.exe and v45h9\driver\Dist\tools\build_inf.exe differ diff -ruN v45h4\driver\Dist\XP\uata_xp.inf v45h9\driver\Dist\XP\uata_xp.inf --- v45h4\driver\Dist\XP\uata_xp.inf Mon Apr 06 17:37:18 2015 +++ v45h9\driver\Dist\XP\uata_xp.inf Wed Sep 23 19:35:40 2015 @@ -6,7 +6,7 @@ ClassGUID={4D36E97B-E325-11CE-BFC1-08002BE10318} Class=SCSIAdapter CatalogFile=uniata.cat -DriverVer=04/06/2015,0.45.8.4 +DriverVer=09/23/2015,0.45.8.9 ; ; Source file information diff -ruN v45h4\driver\Dist\XP\uata_xph.inf v45h9\driver\Dist\XP\uata_xph.inf --- v45h4\driver\Dist\XP\uata_xph.inf Mon Apr 06 17:37:18 2015 +++ v45h9\driver\Dist\XP\uata_xph.inf Wed Sep 23 19:35:40 2015 @@ -6,7 +6,7 @@ ClassGUID={4D36E97B-E325-11CE-BFC1-08002BE10318} Class=hdc CatalogFile=uniata.cat -DriverVer=04/06/2015,0.45.8.4 +DriverVer=09/23/2015,0.45.8.9 ; ; Source file information diff -ruN v45h4\driver\id_ata.cpp v45h9\driver\id_ata.cpp --- v45h4\driver\id_ata.cpp Mon Apr 06 17:02:34 2015 +++ v45h9\driver\id_ata.cpp Wed Sep 23 19:22:54 2015 @@ -267,7 +267,8 @@ return; \ } \ if(res->Proc) { \ - } else \ + ASSERT(FALSE); /* We should never get here */ \ + } \ if(!res->MemIo) { \ ScsiPortWritePort##_Type((_type*)(res->Addr), data); \ } else { \ @@ -302,7 +303,8 @@ return; \ } \ if(res->Proc) { \ - } else \ + ASSERT(FALSE); /* We should never get here */ \ + } \ if(!res->MemIo) { \ ScsiPortWritePort##_Type((_type*)(res->Addr+offs), data); \ } else { \ @@ -335,8 +337,8 @@ return (_type)(-1); \ } \ if(res->Proc) { \ - return 0; \ - } else \ + ASSERT(FALSE); /* We should never get here */ \ + } \ if(!res->MemIo) { \ /*KdPrint(("r_io @ (%x) %x\n", _port, res->Addr));*/ \ return ScsiPortReadPort##_Type((_type*)(res->Addr)); \ @@ -370,8 +372,8 @@ return (_type)(-1); \ } \ if(res->Proc) { \ - return 0; \ - } else \ + ASSERT(FALSE); /* We should never get here */ \ + } \ if(!res->MemIo) { \ return ScsiPortReadPort##_Type((_type*)(res->Addr+offs)); \ } else { \ @@ -796,6 +798,8 @@ { AtapiStallExecution(30); } + KdPrint2((PRINT_PREFIX " set DFLAGS_REINIT_DMA\n")); + chan->lun[DeviceNumber]->DeviceFlags |= DFLAGS_REINIT_DMA; } SelectDrive(chan, DeviceNumber); @@ -1002,22 +1006,27 @@ case ATA_IMMEDIATE: GetStatus(chan, statusByte); if (statusByte & IDE_STATUS_ERROR) { + // Note: some diveces doesn't clear ERR immediately KdPrint2((PRINT_PREFIX " Warning: Immed Status %#x :(\n", statusByte)); if(statusByte == (IDE_STATUS_IDLE | IDE_STATUS_ERROR)) { break; } KdPrint2((PRINT_PREFIX " try to continue\n")); statusByte &= ~IDE_STATUS_ERROR; + + } else { + //KdPrint2((PRINT_PREFIX " send Status %#x\n", statusByte)); } UniataExpectChannelInterrupt(chan, TRUE); // !!!!! InterlockedExchange(&(chan->CheckIntr), CHECK_INTR_IDLE); - statusByte = 0; + + statusByte = IDE_STATUS_SUCCESS; break; } - KdPrint2((PRINT_PREFIX " Status %#x\n", statusByte)); + //KdPrint2((PRINT_PREFIX " Status %#x\n", statusByte)); return statusByte; } // end AtaCommand48() @@ -1298,7 +1307,7 @@ #endif //UNIATA_CORE -#if DBG +#ifdef _DEBUG VOID NTAPI UniataDumpATARegs( @@ -1319,6 +1328,9 @@ chan->RegTranslation[IDX_IO1+j].Addr, statusByteAlt)); } + if(!chan->RegTranslation[IDX_BM_IO].Addr) { + return; + } for(j=0; jAhciInternalAtaReq) { KdPrint2((PRINT_PREFIX "!AhciInternalAtaReq\n")); } @@ -1639,7 +1651,7 @@ if (atapiDev || !(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED) /*!deviceExtension->DWordIO*/) { KdPrint2((PRINT_PREFIX " use 16bit IO\n")); -#if DBG +#ifdef _DEBUG if(atapiDev) { j = (AtapiReadPort1(chan, IDX_ATAPI_IO1_i_InterruptReason) & ATAPI_IR_Mask); KdPrint3((PRINT_PREFIX "IssueIdentify: iReason %x\n", j)); @@ -2023,10 +2035,12 @@ if(NumOfSectors) LunExt->NumOfSectors = NumOfSectors; -/* if(deviceExtension->FullIdentifyData.MajorRevision && + } else { + if(deviceExtension->FullIdentifyData.MajorRevision && deviceExtension->FullIdentifyData.DoubleWordIo) { - LunExt->DeviceFlags |= DFLAGS_DWORDIO_ENABLED; - }*/ + //LunExt->DeviceFlags |= DFLAGS_DWORDIO_ENABLED; + KdPrint2((PRINT_PREFIX "IssueIdentify: DFLAGS_DWORDIO_ENABLED.\n")); + } } ScsiPortMoveMemory(&LunExt->IdentifyData, @@ -2219,7 +2233,7 @@ for (; j < numberChannels; j++) { - KdPrint2((PRINT_PREFIX "AtapiResetController: Reset channel %d\n", j)); + KdPrint2((PRINT_PREFIX "AtapiResetController: Reset lchannel %d[%d]\n", j, deviceExtension->Channel)); chan = &(deviceExtension->chan[j]); MaxLuns = chan->NumberLuns; KdPrint2((PRINT_PREFIX " CompleteType %#x, Luns %d, chan %#x, sptr %#x\n", CompleteType, MaxLuns, chan, &chan)); @@ -2328,7 +2342,7 @@ if(ChipFlags & UNIATA_AHCI) { KdPrint2((PRINT_PREFIX " AHCI path\n")); if(UniataAhciChanImplemented(deviceExtension, j)) { -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif AtapiDisableInterrupts(deviceExtension, j); @@ -2613,6 +2627,7 @@ GetBaseStatus(chan, statusByte); } // force DMA mode reinit + KdPrint2((PRINT_PREFIX " set DFLAGS_REINIT_DMA\n")); chan->lun[i]->DeviceFlags |= DFLAGS_REINIT_DMA; } #endif //0 @@ -4129,7 +4144,7 @@ //SelectDrive(chan, 0); //GetBaseStatus(chan, statusByte); AtapiWritePort1(chan, IDX_IO2_o_Control, - IDE_DC_A_4BIT ); + 0 | IDE_DC_A_4BIT ); //if(chan->NumberLuns) { // SelectDrive(chan, 1); // GetBaseStatus(chan, statusByte); @@ -4942,13 +4957,13 @@ } } else { // We have only Overflow. Abort operation and continue -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif if(!UniataAhciAbortOperation(chan)) { KdPrint2((PRINT_PREFIX "need UniataAhciReset\n")); } -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif UniataAhciWaitCommandReady(chan, 10); @@ -5119,7 +5134,7 @@ if(deviceExtension->HwFlags & UNIATA_AHCI) { error = AtaReq->ahci.in_error; // wait ready -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif if(!UniataAhciAbortOperation(chan)) { @@ -5127,7 +5142,7 @@ } // clear interrupts again UniataAhciWaitCommandReady(chan, 10); -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif UniataAhciStatus(HwDeviceExtension, lChannel, DEVNUM_NOT_SPECIFIED); @@ -5138,7 +5153,7 @@ error |= IDE_STATUS_ERROR; } } -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif } else { @@ -5264,7 +5279,7 @@ LunExt->BlockIoCount )); LunExt->RecoverCount[AtaReq->retry]++; - if(LunExt->RecoverCount[AtaReq->retry] >= chan->lun[DeviceNumber]->BlockIoCount/3 || + if(LunExt->RecoverCount[AtaReq->retry] >= LunExt->BlockIoCount/3 || (deviceExtension->HwFlags & UNIATA_NO80CHK) ) { #else @@ -5403,6 +5418,9 @@ goto CompleteRequest; } else if (interruptReason == ATAPI_IR_COD_Cmd && (statusByte & IDE_STATUS_DRQ)) { + if(chan->ChannelCtrlFlags & CTRFLAGS_DMA_OPERATION) { + AtapiDmaDBPreSync(HwDeviceExtension, chan, srb); + } // Write the packet. KdPrint3((PRINT_PREFIX "AtapiInterrupt: Writing Atapi packet.\n")); // Send CDB to device. @@ -5490,7 +5508,8 @@ statusByte = WaitOnBusy(chan); - if (atapiDev || !(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED) /*!deviceExtension->DWordIO*/) { + if (atapiDev || !(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED) /*!deviceExtension->DWordIO*/ + || (wordCount & 1)) { WriteBuffer(chan, AtaReq->DataBuffer, @@ -5524,7 +5543,7 @@ KdPrint2((PRINT_PREFIX " status %#x, statusByte\n")); if(wordCount) { interruptReason = ATAPI_IR_IO_toHost; -#if DBG +#ifdef _DEBUG UniataDumpATARegs(chan); #endif } @@ -5628,7 +5647,8 @@ statusByte = WaitOnBusy(chan); - if (atapiDev || !(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED) /*!deviceExtension->DWordIO*/) { + if (atapiDev || !(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED) /*!deviceExtension->DWordIO*/ + || (wordCount & 1)) { KdPrint2((PRINT_PREFIX "IdeIntr: Read %#x words\n", wordCount)); @@ -6795,20 +6815,27 @@ if ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) || use_dma) { + if(use_dma) { + AtapiDmaDBPreSync(HwDeviceExtension, chan, Srb); + } statusByte2 = AtaCommand48(deviceExtension, DeviceNumber, lChannel, cmd, lba, (USHORT)(AtaReq->bcount), // (UCHAR)((wordCount*2 + DEV_BSIZE-1) / DEV_BSIZE), 0, ATA_IMMEDIATE); - if(statusByte2 != IDE_STATUS_WRONG) { +/* if(statusByte2 != IDE_STATUS_WRONG) { GetStatus(chan, statusByte2); - } + }*/ if(statusByte2 & IDE_STATUS_ERROR) { + // Unfortunately, we cannot handle errors in such a way in real life (except known bad blocks). + // Because some devices doesn't reset ERR from previous command immediately after getting new one. + // On the other hand we cannot wait here because of possible timeout condition statusByte = AtapiReadPort1(chan, IDX_IO1_i_Error); KdPrint2((PRINT_PREFIX "IdeReadWrite: status %#x, error %#x\n", statusByte2, statusByte)); return SRB_STATUS_ERROR; } if(use_dma) { + //GetStatus(chan, statusByte2); AtapiDmaStart(HwDeviceExtension, DeviceNumber, lChannel, Srb); } return SRB_STATUS_PENDING; @@ -6851,7 +6878,7 @@ CHECK_INTR_IDLE); // Write next DEV_BSIZE/2*N words. - if (!(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED)) { + if (!(LunExt->DeviceFlags & DFLAGS_DWORDIO_ENABLED) || (wordCount & 1)) { KdPrint2((PRINT_PREFIX "IdeReadWrite: Write %#x words\n", wordCount)); @@ -7730,11 +7757,14 @@ // clear interrupt GetBaseStatus(chan, statusByte); -#if DBG +#ifdef _DEBUG statusByte = (AtapiReadPort1(chan, IDX_ATAPI_IO1_i_InterruptReason) & ATAPI_IR_Mask); KdPrint3((PRINT_PREFIX "AtapiSendCommand: iReason %x\n", statusByte)); #endif //DBG + if(chan->ChannelCtrlFlags & CTRFLAGS_DMA_OPERATION) { + AtapiDmaDBPreSync(HwDeviceExtension, chan, Srb); + } if(g_opt_AtapiSendDisableIntr) { AtapiEnableInterrupts(deviceExtension, lChannel); } @@ -8044,7 +8074,11 @@ } else { RtlZeroMemory(modeData, sizeof(MODE_POWER_CONDITION_PAGE)); modeData->PageCode = MODE_PAGE_POWER_CONDITION; +#ifdef __REACTOS__ + modeData->PageLength = sizeof(MODE_POWER_CONDITION_PAGE)-sizeof(MODE_PARAMETER_HEADER); +#else modeData->PageLength = sizeof(MODE_PAGE_POWER_CONDITION)-sizeof(MODE_PARAMETER_HEADER); +#endif modeData->Byte3.Fields.Idle = LunExt->PowerState <= StartStop_Power_Idle; modeData->Byte3.Fields.Standby = LunExt->PowerState == StartStop_Power_Standby; Srb->DataTransferLength = sizeof(MODE_POWER_CONDITION_PAGE); @@ -8478,6 +8512,9 @@ AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, regs->bDriveHeadReg); AtapiStallExecution(10); + if(use_dma) { + AtapiDmaDBPreSync(HwDeviceExtension, chan, Srb); + } if((regs->bOpFlags & ATA_FLAGS_48BIT_COMMAND) == 0) { // execute ATA command AtapiWritePort1(chan, IDX_IO1_o_Feature, regs->bFeaturesReg); @@ -10217,7 +10254,7 @@ return status; } #endif // USE_REACTOS_DDK - KdPrint(("UniATA Init: OS ver %x.%x (%d), %d CPU(s)\n", MajorVersion, MinorVersion, BuildNumber, KeNumberProcessors)); + KdPrint(("UniATA Init: OS ver %x.%x (%d), %d CPU(s)\n", MajorVersion, MinorVersion, BuildNumber, *KeNumberProcessors)); KeQuerySystemTime(&t0); do { diff -ruN v45h4\driver\id_dma.cpp v45h9\driver\id_dma.cpp --- v45h4\driver\id_dma.cpp Mon Apr 06 17:33:04 2015 +++ v45h9\driver\id_dma.cpp Wed Sep 23 19:12:12 2015 @@ -1,6 +1,6 @@ /*++ -Copyright (c) 2002-2014 Alexander A. Telyatnikov (Alter) +Copyright (c) 2002-2015 Alexander A. Telyatnikov (Alter) Module Name: id_dma.cpp @@ -539,6 +539,41 @@ return TRUE; } // end AtapiDmaDBSync() +BOOLEAN +NTAPI +AtapiDmaDBPreSync( + IN PVOID HwDeviceExtension, + PHW_CHANNEL chan, + PSCSI_REQUEST_BLOCK Srb + ) +{ + PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension; + PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension); + + if(!AtaReq->ata.dma_base) { + KdPrint2((PRINT_PREFIX "AtapiDmaDBPreSync: *** !AtaReq->ata.dma_base\n")); + return FALSE; + } +// GetStatus(chan, statusByte2); + if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) { + KdPrint2((PRINT_PREFIX " DBUF_PRD\n")); + ASSERT(FALSE); + if(deviceExtension->HwFlags & UNIATA_AHCI) { + RtlCopyMemory(chan->DB_PRD, AtaReq->ahci.ahci_cmd_ptr, sizeof(AtaReq->ahci_cmd0)); + } else { + RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab)); + } + } + if(!(Srb->SrbFlags & SRB_FLAGS_DATA_IN) && + (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) { + KdPrint2((PRINT_PREFIX " DBUF (Write)\n")); + ASSERT(FALSE); + RtlCopyMemory(chan->DB_IO, AtaReq->DataBuffer, + Srb->DataTransferLength); + } + return TRUE; +} // end AtapiDmaDBPreSync() + VOID NTAPI AtapiDmaStart( @@ -555,15 +590,20 @@ ULONG VendorID = deviceExtension->DevID & 0xffff; ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK; - +// UCHAR statusByte2; +/* + GetStatus(chan, statusByte2); KdPrint2((PRINT_PREFIX "AtapiDmaStart: %s on %#x:%#x\n", (Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? "read" : "write", lChannel, DeviceNumber )); - +*/ if(!AtaReq->ata.dma_base) { KdPrint2((PRINT_PREFIX "AtapiDmaStart: *** !AtaReq->ata.dma_base\n")); return; } + +/* +// GetStatus(chan, statusByte2); if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) { KdPrint2((PRINT_PREFIX " DBUF_PRD\n")); ASSERT(FALSE); @@ -580,7 +620,7 @@ RtlCopyMemory(chan->DB_IO, AtaReq->DataBuffer, Srb->DataTransferLength); } - +*/ // set flag chan->ChannelCtrlFlags |= CTRFLAGS_DMA_ACTIVE; @@ -792,6 +832,9 @@ KdPrint2((PRINT_PREFIX "AtapiDmaReinit: restore IO mode on Device %d\n", LunExt->Lun)); AtapiDmaInit__(deviceExtension, LunExt); + } else { + KdPrint2((PRINT_PREFIX + "AtapiDmaReinit: LimitedTransferMode == TransferMode = %x (%x)\n", LunExt->TransferMode, LunExt->DeviceFlags)); } exit: @@ -1436,6 +1479,7 @@ /* Intel */ /*********/ + KdPrint2((PRINT_PREFIX "Intel %d\n", Channel)); BOOLEAN udma_ok = FALSE; ULONG idx = 0; ULONG reg40; @@ -1452,6 +1496,7 @@ UCHAR intel_utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; if(deviceExtension->DevID == ATA_I82371FB) { + KdPrint2((PRINT_PREFIX " I82371FB\n")); if (wdmamode >= 2 && apiomode >= 4) { ULONG word40; @@ -1474,6 +1519,7 @@ if(deviceExtension->DevID == ATA_ISCH) { ULONG tim; + KdPrint2((PRINT_PREFIX " ISCH\n")); GetPciConfig4(0x80 + dev*4, tim); for(i=udmamode; i>=0; i--) { @@ -1557,6 +1603,7 @@ udma_ok = TRUE; idx = i+8; if(ChipFlags & ICH4_FIX) { + KdPrint2((PRINT_PREFIX " ICH4_FIX udma\n")); return; } break; @@ -1574,6 +1621,7 @@ udma_ok = TRUE; idx = i+5; if(ChipFlags & ICH4_FIX) { + KdPrint2((PRINT_PREFIX " ICH4_FIX wdma\n")); return; } break; @@ -1590,17 +1638,19 @@ GetPciConfig1(0x44, reg44); /* Allow PIO/WDMA timing controls. */ + reg40 &= ~0x00ff00ff; + reg40 |= 0x40774077; + mask40 = 0x000000ff; /* Set PIO/WDMA timings. */ if(!(DeviceNumber & 1)) { - mask40 |= 0x00003300; + mask40 = 0x00003300; new40 = ((USHORT)(intel_timings[idx]) << 8); } else { mask44 = 0x0f; new44 = ((intel_timings[idx] & 0x30) >> 2) | (intel_timings[idx] & 0x03); } - new40 |= 0x00004077; if (Channel) { mask40 <<= 16; @@ -1609,6 +1659,7 @@ new44 <<= 4; } + KdPrint2((PRINT_PREFIX " 0x40 %x/%x, 0x44 %x/%x\n", mask40, new40, mask44, new44)); SetPciConfig4(0x40, (reg40 & ~mask40) | new40); SetPciConfig1(0x44, (reg44 & ~mask44) | new44); diff -ruN v45h4\driver\id_init.cpp v45h9\driver\id_init.cpp --- v45h4\driver\id_init.cpp Tue Feb 24 01:49:38 2015 +++ v45h9\driver\id_init.cpp Wed Sep 23 02:09:36 2015 @@ -397,8 +397,6 @@ if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) { return STATUS_UNSUCCESSFUL; } - // DEBUG, we shall return success when AHCI is completly supported - //return STATUS_NOT_FOUND; return STATUS_SUCCESS; } @@ -570,8 +568,7 @@ ScsiPortFreeDeviceBase(HwDeviceExtension, deviceExtension->BaseIoAddressBM_0); - deviceExtension->BaseIoAddressBM_0.Addr = 0; - deviceExtension->BaseIoAddressBM_0.MemIo = 0; + UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, 0, FALSE, FALSE); deviceExtension->BusMaster = DMA_MODE_NONE; deviceExtension->MaxTransferMode = ATA_PIO4; break; @@ -682,13 +679,13 @@ chan = &deviceExtension->chan[c]; for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].Addr = BaseIoAddress1 + i + (unit10 ? 8 : 0); + UniataInitIoRes(chan, IDX_IO1+i, BaseIoAddress1 + i + (unit10 ? 8 : 0), FALSE, FALSE); } - chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseIoAddress2 + 2 + (unit10 ? 4 : 0); + UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseIoAddress2 + 2 + (unit10 ? 4 : 0), FALSE, FALSE); UniataInitSyncBaseIO(chan); for (i=0; i<=IDX_BM_IO_SZ; i++) { - chan->RegTranslation[IDX_BM_IO+i].Addr = BaseIoAddressBM + i + (c * sizeof(IDE_BUSMASTER_REGISTERS)); + UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM + i + (c * sizeof(IDE_BUSMASTER_REGISTERS)), FALSE, FALSE); } // SATA not supported yet @@ -714,17 +711,13 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); for(c=0; cNumberChannels; c++) { chan = &deviceExtension->chan[c]; - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + (c << 6); - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 4 + (c << 6); - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 8 + (c << 6); - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + (c << 6), MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + (c << 6), MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + (c << 6), MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } @@ -751,8 +744,7 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); /* BAR3 -> res2 */ BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, @@ -765,8 +757,7 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressBM_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressBM_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, BaseMemAddress, MemIo, FALSE); if(!(ChipFlags & UNIATA_SATA)) { UCHAR reg48; @@ -789,31 +780,23 @@ offs7 = c << 7; for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].Addr = BaseMemAddress + 0x200 + (i << 2) + offs7; - chan->RegTranslation[IDX_IO1+i].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + 0x200 + (i << 2) + offs8, MemIo, FALSE); } - chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseMemAddress + 0x238 + offs7; - chan->RegTranslation[IDX_IO2_AltStatus].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x238 + offs7, MemIo, FALSE); UniataInitSyncBaseIO(chan); - chan->RegTranslation[IDX_BM_Command].Addr = BaseMemAddress + 0x260 + offs7; - chan->RegTranslation[IDX_BM_Command].MemIo = MemIo; - chan->RegTranslation[IDX_BM_PRD_Table].Addr = BaseMemAddress + 0x244 + offs7; - chan->RegTranslation[IDX_BM_PRD_Table].MemIo = MemIo; - chan->RegTranslation[IDX_BM_DeviceSpecific0].Addr = BaseMemAddress + (c << 2); - chan->RegTranslation[IDX_BM_DeviceSpecific0].MemIo = MemIo; + UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x260 + offs7, MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x244 + offs7, MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_DeviceSpecific0, BaseMemAddress + (c << 2), MemIo, FALSE); if((ChipFlags & PRSATA) || ((ChipFlags & PRCMBO) && c<2)) { KdPrint2((PRINT_PREFIX "Promise SATA\n")); - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0x400 + offs7; - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 0x404 + offs7; - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 0x408 + offs7; - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x400 + offs7, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x404 + offs7, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x408 + offs7, MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } else { @@ -864,8 +847,7 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); for(c=0; cNumberChannels; c++) { ULONG unit01 = (c & 1); @@ -875,25 +857,16 @@ if(deviceExtension->AltRegMap) { for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].Addr = BaseMemAddress + 0x80 + i + (unit01 << 6) + (unit10 << 8); - chan->RegTranslation[IDX_IO1+i].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + 0x80 + i + (unit01 << 6) + (unit10 << 8), MemIo, FALSE); } - chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseMemAddress + 0x8a + (unit01 << 6) + (unit10 << 8); - chan->RegTranslation[IDX_IO2_AltStatus].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x8a + (unit01 << 6) + (unit10 << 8), MemIo, FALSE); UniataInitSyncBaseIO(chan); - chan->RegTranslation[IDX_BM_Command].Addr = BaseMemAddress + 0x00 + (unit01 << 3) + (unit10 << 8); - chan->RegTranslation[IDX_BM_Command].MemIo = MemIo; - chan->RegTranslation[IDX_BM_Status].Addr = BaseMemAddress + 0x02 + (unit01 << 3) + (unit10 << 8); - chan->RegTranslation[IDX_BM_Status].MemIo = MemIo; - chan->RegTranslation[IDX_BM_PRD_Table].Addr = BaseMemAddress + 0x04 + (unit01 << 3) + (unit10 << 8); - chan->RegTranslation[IDX_BM_PRD_Table].MemIo = MemIo; - //chan->RegTranslation[IDX_BM_DeviceSpecific0].Addr = BaseMemAddress + 0xa1 + (unit01 << 6) + (unit10 << 8); - //chan->RegTranslation[IDX_BM_DeviceSpecific0].MemIo = MemIo; - chan->RegTranslation[IDX_BM_DeviceSpecific0].Addr = BaseMemAddress + 0x10 + (unit01 << 3) + (unit10 << 8); - chan->RegTranslation[IDX_BM_DeviceSpecific0].MemIo = MemIo; - chan->RegTranslation[IDX_BM_DeviceSpecific1].Addr = BaseMemAddress + 0x40 + (unit01 << 2) + (unit10 << 8); - chan->RegTranslation[IDX_BM_DeviceSpecific1].MemIo = MemIo; + UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x00 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + 0x02 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x04 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_DeviceSpecific0, BaseMemAddress + 0x10 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_DeviceSpecific1, BaseMemAddress + 0x40 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE); } if(chan->MaxTransferMode < ATA_SA150) { @@ -901,12 +874,9 @@ KdPrint2((PRINT_PREFIX "No SATA regs for PATA part\n")); } else if(ChipFlags & UNIATA_SATA) { - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0x104 + (unit01 << 7) + (unit10 << 8); - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 0x108 + (unit01 << 7) + (unit10 << 8); - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 0x100 + (unit01 << 7) + (unit10 << 8); - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x104 + (unit01 << 7) + (unit10 << 8), MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x108 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x100 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } @@ -935,34 +905,25 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); for(c=0; cNumberChannels; c++) { ULONG offs = c*0x100; chan = &deviceExtension->chan[c]; for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].Addr = BaseMemAddress + offs + i*4; - chan->RegTranslation[IDX_IO1+i].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + offs + i*4, MemIo, FALSE); } - chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseMemAddress + offs + 0x20; - chan->RegTranslation[IDX_IO2_AltStatus].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + offs + 0x20, MemIo, FALSE); UniataInitSyncBaseIO(chan); - chan->RegTranslation[IDX_BM_Command].Addr = BaseMemAddress + offs + 0x30; - chan->RegTranslation[IDX_BM_Command].MemIo = MemIo; - chan->RegTranslation[IDX_BM_Status].Addr = BaseMemAddress + offs + 0x32; - chan->RegTranslation[IDX_BM_Status].MemIo = MemIo; - chan->RegTranslation[IDX_BM_PRD_Table].Addr = BaseMemAddress + offs + 0x34; - chan->RegTranslation[IDX_BM_PRD_Table].MemIo = MemIo; - - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + offs + 0x40; - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + offs + 0x44; - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + offs + 0x48; - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + offs + 0x30, MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + offs + 0x32, MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + offs + 0x34, MemIo, FALSE); + + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + offs + 0x40, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + offs + 0x44, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + offs + 0x48, MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } @@ -1039,19 +1000,15 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); for(c=0; cNumberChannels; c++) { ULONG offs = c << (SIS_182 ? 5 : 6); chan = &deviceExtension->chan[c]; - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0 + offs; - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 4 + offs; - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 8 + offs; - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + offs, MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } @@ -1092,8 +1049,7 @@ KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); } if(/*deviceExtension->*/BaseMemAddress) { KdPrint2((PRINT_PREFIX "UniataChipDetect: BAR5 %x\n", /*deviceExtension->*/BaseMemAddress)); @@ -1114,13 +1070,13 @@ BaseIo = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, c, 0, /*0x80*/ sizeof(IDE_REGISTERS_1) + sizeof(IDE_REGISTERS_2)*2); for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].Addr = BaseIo + i; + UniataInitIoRes(chan, IDX_IO1+i, BaseIo + i, FALSE, FALSE); } - chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseIo + sizeof(IDE_REGISTERS_1) + 2; + UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseIo + sizeof(IDE_REGISTERS_1) + 2, FALSE, FALSE); UniataInitSyncBaseIO(chan); for (i=0; i<=IDX_BM_IO_SZ; i++) { - chan->RegTranslation[IDX_BM_IO+i].Addr = BaseIoAddressBM_0 + sizeof(IDE_BUSMASTER_REGISTERS)*c + i; + UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM_0 + sizeof(IDE_BUSMASTER_REGISTERS)*c + i, FALSE, FALSE); } } @@ -1130,17 +1086,13 @@ if((ChipFlags & VIABAR) && (c==2)) { // Do not setup SATA registers for PATA part for (i=0; i<=IDX_SATA_IO_SZ; i++) { - chan->RegTranslation[IDX_SATA_IO+i].Addr = 0; - chan->RegTranslation[IDX_SATA_IO+i].MemIo = 0; + UniataInitIoRes(chan, IDX_SATA_IO+i, 0, FALSE, FALSE); } break; } - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + (c * IoSize); - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 4 + (c * IoSize); - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 8 + (c * IoSize); - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + (c * IoSize), MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + (c * IoSize), MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + (c * IoSize), MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } @@ -1169,49 +1121,31 @@ MemIo = TRUE; } deviceExtension->AltRegMap = TRUE; // inform generic resource allocator - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); for(c=0; cNumberChannels; c++) { ULONG offs = 0x200 + c*0x200; chan = &deviceExtension->chan[c]; for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].MemIo = MemIo; - chan->RegTranslation[IDX_IO1_o+i].MemIo = MemIo; + UniataInitIoRes(chan, IDX_BM_IO+i, BaseMemAddress + i*4 + offs, MemIo, FALSE); } - chan->RegTranslation[IDX_IO1_i_Data ].Addr = BaseMemAddress + 0x00 + offs; - chan->RegTranslation[IDX_IO1_i_Error ].Addr = BaseMemAddress + 0x04 + offs; - chan->RegTranslation[IDX_IO1_i_BlockCount ].Addr = BaseMemAddress + 0x08 + offs; - chan->RegTranslation[IDX_IO1_i_BlockNumber ].Addr = BaseMemAddress + 0x0c + offs; - chan->RegTranslation[IDX_IO1_i_CylinderLow ].Addr = BaseMemAddress + 0x10 + offs; - chan->RegTranslation[IDX_IO1_i_CylinderHigh].Addr = BaseMemAddress + 0x14 + offs; - chan->RegTranslation[IDX_IO1_i_DriveSelect ].Addr = BaseMemAddress + 0x18 + offs; - chan->RegTranslation[IDX_IO1_i_Status ].Addr = BaseMemAddress + 0x1c + offs; - UniataInitSyncBaseIO(chan); - chan->RegTranslation[IDX_IO1_o_Command ].Addr = BaseMemAddress + 0x1d + offs; - chan->RegTranslation[IDX_IO1_o_Feature ].Addr = BaseMemAddress + 0x06 + offs; - chan->RegTranslation[IDX_IO2_o_Control ].Addr = BaseMemAddress + 0x29 + offs; - - chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseMemAddress + 0x28 + offs; - chan->RegTranslation[IDX_IO2_AltStatus].MemIo = MemIo; - - chan->RegTranslation[IDX_BM_Command].Addr = BaseMemAddress + offs + 0x70; - chan->RegTranslation[IDX_BM_Command].MemIo = MemIo; - chan->RegTranslation[IDX_BM_Status].Addr = BaseMemAddress + offs + 0x72; - chan->RegTranslation[IDX_BM_Status].MemIo = MemIo; - chan->RegTranslation[IDX_BM_PRD_Table].Addr = BaseMemAddress + offs + 0x74; - chan->RegTranslation[IDX_BM_PRD_Table].MemIo = MemIo; - - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0x100 + offs; - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 0x104 + offs; - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 0x108 + offs; - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + UniataInitIoRes(chan, IDX_IO1_o_Command, BaseMemAddress + 0x1d + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_IO1_o_Feature, BaseMemAddress + 0x06 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_IO2_o_Control, BaseMemAddress + 0x29 + offs, MemIo, FALSE); + + UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x28 + offs, MemIo, FALSE); + + UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x70 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + 0x72 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x74 + offs, MemIo, FALSE); + + UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x100 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x104 + offs, MemIo, FALSE); + UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x108 + offs, MemIo, FALSE); chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; } @@ -1243,15 +1177,13 @@ KdPrint2((PRINT_PREFIX "MemIo[4]\n")); MemIo = TRUE; } - deviceExtension->BaseIoAddressBM_0.Addr = BaseIoAddressBM; - deviceExtension->BaseIoAddressBM_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, BaseIoAddressBM, MemIo, FALSE); tmp8 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),IDX_BM_Status); KdPrint2((PRINT_PREFIX "BM status: %x\n", tmp8)); /* cleanup */ ScsiPortFreeDeviceBase(HwDeviceExtension, (PCHAR)BaseIoAddressBM); - deviceExtension->BaseIoAddressBM_0.Addr = 0; - deviceExtension->BaseIoAddressBM_0.MemIo = 0; + UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, 0, 0, FALSE); if(tmp8 == 0xff) { KdPrint2((PRINT_PREFIX "invalid BM status, keep AHCI mode\n")); @@ -1287,8 +1219,7 @@ MemIo = TRUE; } } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE); for(c=0; cNumberChannels; c++) { chan = &deviceExtension->chan[c]; @@ -1337,10 +1268,8 @@ if(!(ChipFlags & ICH7) && BaseMemAddress) { KdPrint2((PRINT_PREFIX "BaseMemAddress[5] -> indexed\n")); - chan->RegTranslation[IDX_INDEXED_ADDR].Addr = BaseMemAddress + 0; - chan->RegTranslation[IDX_INDEXED_ADDR].MemIo = MemIo; - chan->RegTranslation[IDX_INDEXED_DATA].Addr = BaseMemAddress + 4; - chan->RegTranslation[IDX_INDEXED_DATA].MemIo = MemIo; + UniataInitIoRes(chan, IDX_INDEXED_ADDR, BaseMemAddress + 0, MemIo, FALSE); + UniataInitIoRes(chan, IDX_INDEXED_DATA, BaseMemAddress + 4, MemIo, FALSE); } if((ChipFlags & ICH5) || BaseMemAddress) { @@ -1353,12 +1282,9 @@ if(ChipFlags & ICH7) { KdPrint2((PRINT_PREFIX "ICH7 way\n")); } - chan->RegTranslation[IDX_SATA_SStatus].Addr = 0x200*c + 0; // this is fake non-zero value - chan->RegTranslation[IDX_SATA_SStatus].Proc = 1; - chan->RegTranslation[IDX_SATA_SError].Addr = 0x200*c + 2; // this is fake non-zero value - chan->RegTranslation[IDX_SATA_SError].Proc = 1; - chan->RegTranslation[IDX_SATA_SControl].Addr = 0x200*c + 1; // this is fake non-zero value - chan->RegTranslation[IDX_SATA_SControl].Proc = 1; + UniataInitIoRes(chan, IDX_SATA_SStatus, 0x200*c + 0, FALSE, TRUE); // this is fake non-zero value + UniataInitIoRes(chan, IDX_SATA_SError, 0x200*c + 2, FALSE, TRUE); + UniataInitIoRes(chan, IDX_SATA_SControl, 0x200*c + 1, FALSE, TRUE); } } @@ -2713,8 +2639,7 @@ for(c=0; cNumberChannels; c++) { chan = &deviceExtension->chan[c]; for (i=0; iRegTranslation[IDX_BM_IO+i].Addr = BaseIoAddressBM_0 ? ((ULONGIO_PTR)BaseIoAddressBM_0 + i) : 0; - chan->RegTranslation[IDX_BM_IO+i].MemIo = MemIo; + UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM_0 ? ((ULONGIO_PTR)BaseIoAddressBM_0 + i) : 0, MemIo, FALSE); } if(BaseIoAddressBM_0) { BaseIoAddressBM_0++; @@ -2734,12 +2659,10 @@ ULONG i; for (i=0; iRegTranslation[IDX_IO1+i].Addr = BaseIoAddress1 ? ((ULONGIO_PTR)BaseIoAddress1 + i) : 0; - chan->RegTranslation[IDX_IO1+i].MemIo = FALSE; + UniataInitIoRes(chan, IDX_IO1+i, BaseIoAddress1 ? ((ULONGIO_PTR)BaseIoAddress1 + i) : 0, FALSE, FALSE); } for (i=0; iRegTranslation[IDX_IO2+i].Addr = BaseIoAddress2 ? ((ULONGIO_PTR)BaseIoAddress2 + i) : 0; - chan->RegTranslation[IDX_IO2+i].MemIo = FALSE; + UniataInitIoRes(chan, IDX_IO2+i, BaseIoAddress2 ? ((ULONGIO_PTR)BaseIoAddress2 + i) : 0, FALSE, FALSE); } UniataInitSyncBaseIO(chan); return; @@ -2755,6 +2678,39 @@ RtlCopyMemory(&chan->RegTranslation[IDX_IO2_o], &chan->RegTranslation[IDX_IO2], IDX_IO2_SZ*sizeof(chan->RegTranslation[0])); return; } // end UniataInitSyncBaseIO() + +VOID +UniataInitIoRes( + IN PHW_CHANNEL chan, + IN ULONG idx, + IN ULONG addr, + IN BOOLEAN MemIo, + IN BOOLEAN Proc + ) +{ + if(!addr) { + MemIo = Proc = FALSE; + } + chan->RegTranslation[idx].Addr = addr; + chan->RegTranslation[idx].MemIo = MemIo; + chan->RegTranslation[idx].Proc = Proc; +} // end UniataInitIoRes() + +VOID +UniataInitIoResEx( + IN PIORES IoRes, + IN ULONG addr, + IN BOOLEAN MemIo, + IN BOOLEAN Proc + ) +{ + if(!addr) { + MemIo = Proc = FALSE; + } + IoRes->Addr = addr; + IoRes->MemIo = MemIo; + IoRes->Proc = Proc; +} // end UniataInitIoResEx() VOID NTAPI diff -ruN v45h4\driver\id_probe.cpp v45h9\driver\id_probe.cpp --- v45h4\driver\id_probe.cpp Sun Feb 22 23:26:36 2015 +++ v45h9\driver\id_probe.cpp Wed Sep 23 18:18:20 2015 @@ -297,6 +297,7 @@ // PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension; // PVOID HwDeviceExtension; PHW_DEVICE_EXTENSION deviceExtension = NULL; + PCHAR PciDevMap = NULL; PCI_SLOT_NUMBER slotData; PCI_COMMON_CONFIG pciData; ULONG busNumber; @@ -336,12 +337,20 @@ deviceStrPtr = deviceString; slotData.u.AsULONG = 0; + if(!maxPciBus) { + return(SP_RETURN_NOT_FOUND); + } /*HwDeviceExtension =*/ deviceExtension = (PHW_DEVICE_EXTENSION)ExAllocatePool(NonPagedPool, sizeof(HW_DEVICE_EXTENSION)); if(!deviceExtension) { return(SP_RETURN_NOT_FOUND); } RtlZeroMemory(deviceExtension, sizeof(HW_DEVICE_EXTENSION)); + PciDevMap = (PCHAR)ExAllocatePool(NonPagedPool, maxPciBus*PCI_MAX_DEVICES); + if(!PciDevMap) { + goto exit; + } + RtlZeroMemory(PciDevMap, maxPciBus*PCI_MAX_DEVICES); for(pass=0; pass<3; pass++) { for(busNumber=0 ;busNumber 31*/ || + (IrqForCompat == 0xff)) { + IrqForCompat = 0x0b; + KdPrint2((PRINT_PREFIX "default to IRQ 11\n")); } - if(AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"NativePCIMode", 0)) { - KdPrint2((PRINT_PREFIX "try switch to native mode\n")); - IrqForCompat = (UCHAR)AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"NativePCIModeIRQ", 0xff); - KdPrint2((PRINT_PREFIX "IrqForCompat = %#x\n", IrqForCompat)); - if((IrqForCompat & 0xffffff00) /*|| - (IrqForCompat & 0xff) > 31*/ || - (IrqForCompat == 0xff)) { - IrqForCompat = 0x0b; - KdPrint2((PRINT_PREFIX "default to IRQ 11\n")); + //ChangePciConfig1(0x09, a | PCI_IDE_PROGIF_NATIVE_ALL); // ProgIf + pciData.ProgIf |= PCI_IDE_PROGIF_NATIVE_ALL; + HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, + &(pciData.ProgIf), + offsetof(PCI_COMMON_CONFIG, ProgIf), + sizeof(pciData.ProgIf)); + + // reread config space + busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotData.u.AsULONG, + &pciData, PCI_COMMON_HDR_LENGTH); + // check if the device have switched to Native Mode + if(IsMasterDev(&pciData)) { + KdPrint2((PRINT_PREFIX "Can't switch to native mode\n")); + } else { + KdPrint2((PRINT_PREFIX "switched to native mode\n")); + KdPrint2((PRINT_PREFIX "InterruptPin = %#x\n", pciData.u.type0.InterruptPin)); + KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData.u.type0.InterruptLine)); + // check if IRQ is assigned to device + if(!(pciData.u.type0.InterruptLine) || + (pciData.u.type0.InterruptLine == 0xff)) { + KdPrint2((PRINT_PREFIX "assign interrupt for device\n")); + pciData.u.type0.InterruptLine = IrqForCompat; + HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, + &(pciData.u.type0.InterruptLine), + offsetof(PCI_COMMON_CONFIG, u.type0.InterruptLine), + sizeof(pciData.u.type0.InterruptLine)); + } else { + KdPrint2((PRINT_PREFIX "Auto-assigned interrupt line %#x\n", + pciData.u.type0.InterruptLine)); + IrqForCompat = pciData.u.type0.InterruptLine; } - - //ChangePciConfig1(0x09, a | PCI_IDE_PROGIF_NATIVE_ALL); // ProgIf - pciData.ProgIf |= PCI_IDE_PROGIF_NATIVE_ALL; - HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, - &(pciData.ProgIf), - offsetof(PCI_COMMON_CONFIG, ProgIf), - sizeof(pciData.ProgIf)); - + KdPrint2((PRINT_PREFIX "reread config space\n")); // reread config space busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotData.u.AsULONG, &pciData, PCI_COMMON_HDR_LENGTH); - // check if the device have switched to Native Mode - if(IsMasterDev(&pciData)) { - KdPrint2((PRINT_PREFIX "Can't switch to native mode\n")); - } else { - KdPrint2((PRINT_PREFIX "switched to native mode\n")); - KdPrint2((PRINT_PREFIX "InterruptPin = %#x\n", pciData.u.type0.InterruptPin)); - KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData.u.type0.InterruptLine)); - // check if IRQ is assigned to device - if(!(pciData.u.type0.InterruptLine) || - (pciData.u.type0.InterruptLine == 0xff)) { - KdPrint2((PRINT_PREFIX "assign interrupt for device\n")); - pciData.u.type0.InterruptLine = IrqForCompat; - HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, - &(pciData.u.type0.InterruptLine), - offsetof(PCI_COMMON_CONFIG, u.type0.InterruptLine), - sizeof(pciData.u.type0.InterruptLine)); - } else { - KdPrint2((PRINT_PREFIX "Auto-assigned interrupt line %#x\n", - pciData.u.type0.InterruptLine)); - IrqForCompat = pciData.u.type0.InterruptLine; - } - KdPrint2((PRINT_PREFIX "reread config space\n")); + KdPrint2((PRINT_PREFIX "busDataRead = %#x\n", busDataRead)); + KdPrint2((PRINT_PREFIX "reread InterruptLine = %#x\n", pciData.u.type0.InterruptLine)); + // check if we have successfully assigned IRQ to device + if((pciData.u.type0.InterruptLine != IrqForCompat) || + (pciData.u.type0.InterruptLine == 0xff) || + !pciData.u.type0.InterruptLine) { + KdPrint2((PRINT_PREFIX "can't assign interrupt for device, revert to compat mode\n")); + pciData.u.type0.InterruptLine = 0xff; + KdPrint2((PRINT_PREFIX "set IntrLine to 0xff\n")); + HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, + &(pciData.u.type0.InterruptLine), + offsetof(PCI_COMMON_CONFIG, u.type0.InterruptLine), + sizeof(pciData.u.type0.InterruptLine)); + KdPrint2((PRINT_PREFIX "clear PCI_IDE_PROGIF_NATIVE_ALL\n")); + pciData.ProgIf &= ~PCI_IDE_PROGIF_NATIVE_ALL; + HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, + &(pciData.ProgIf), + offsetof(PCI_COMMON_CONFIG, ProgIf), + sizeof(pciData.ProgIf)); // reread config space + KdPrint2((PRINT_PREFIX "reread config space on revert\n")); busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotData.u.AsULONG, &pciData, PCI_COMMON_HDR_LENGTH); - KdPrint2((PRINT_PREFIX "busDataRead = %#x\n", busDataRead)); - KdPrint2((PRINT_PREFIX "reread InterruptLine = %#x\n", pciData.u.type0.InterruptLine)); - // check if we have successfully assigned IRQ to device - if((pciData.u.type0.InterruptLine != IrqForCompat) || - (pciData.u.type0.InterruptLine == 0xff) || - !pciData.u.type0.InterruptLine) { - KdPrint2((PRINT_PREFIX "can't assign interrupt for device, revert to compat mode\n")); - pciData.u.type0.InterruptLine = 0xff; - KdPrint2((PRINT_PREFIX "set IntrLine to 0xff\n")); - HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, - &(pciData.u.type0.InterruptLine), - offsetof(PCI_COMMON_CONFIG, u.type0.InterruptLine), - sizeof(pciData.u.type0.InterruptLine)); - KdPrint2((PRINT_PREFIX "clear PCI_IDE_PROGIF_NATIVE_ALL\n")); - pciData.ProgIf &= ~PCI_IDE_PROGIF_NATIVE_ALL; - HalSetBusDataByOffset( PCIConfiguration, busNumber, slotData.u.AsULONG, - &(pciData.ProgIf), - offsetof(PCI_COMMON_CONFIG, ProgIf), - sizeof(pciData.ProgIf)); - // reread config space - KdPrint2((PRINT_PREFIX "reread config space on revert\n")); - busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotData.u.AsULONG, - &pciData, PCI_COMMON_HDR_LENGTH); - } else { - KdPrint2((PRINT_PREFIX "Assigned interrupt %#x for device\n", IrqForCompat)); - KdPrint2((PRINT_PREFIX "continue detection on next round\n")); - continue; - } + } else { + KdPrint2((PRINT_PREFIX "Assigned interrupt %#x for device\n", IrqForCompat)); + KdPrint2((PRINT_PREFIX "continue detection on next round\n")); + continue; } } - } else - if(pass == 2) { - if(IsMasterDev(&pciData)) - continue; } + } else + if(pass == 2) { + if(IsMasterDev(&pciData)) + continue; + } /* if(known) { - RtlCopyMemory(newBMListPtr, (PVOID)&(BusMasterAdapters[i]), sizeof(BUSMASTER_CONTROLLER_INFORMATION)); - } else {*/ - sprintf((PCHAR)vendorStrPtr, "%4.4lx", VendorID); - sprintf((PCHAR)deviceStrPtr, "%4.4lx", DeviceID); - - RtlCopyMemory(&(newBMListPtr->VendorIdStr), (PCHAR)vendorStrPtr, 4); - RtlCopyMemory(&(newBMListPtr->DeviceIdStr), (PCHAR)deviceStrPtr, 4); - - newBMListPtr->nVendorId = VendorID; - newBMListPtr->VendorId = (PCHAR)&(newBMListPtr->VendorIdStr); - newBMListPtr->VendorIdLength = 4; - newBMListPtr->nDeviceId = DeviceID; - newBMListPtr->DeviceId = (PCHAR)&(newBMListPtr->DeviceIdStr); - newBMListPtr->DeviceIdLength = 4; + RtlCopyMemory(newBMListPtr, (PVOID)&(BusMasterAdapters[i]), sizeof(BUSMASTER_CONTROLLER_INFORMATION)); + } else {*/ + sprintf((PCHAR)vendorStrPtr, "%4.4lx", VendorID); + sprintf((PCHAR)deviceStrPtr, "%4.4lx", DeviceID); + + RtlCopyMemory(&(newBMListPtr->VendorIdStr), (PCHAR)vendorStrPtr, 4); + RtlCopyMemory(&(newBMListPtr->DeviceIdStr), (PCHAR)deviceStrPtr, 4); + + newBMListPtr->nVendorId = VendorID; + newBMListPtr->VendorId = (PCHAR)&(newBMListPtr->VendorIdStr); + newBMListPtr->VendorIdLength = 4; + newBMListPtr->nDeviceId = DeviceID; + newBMListPtr->DeviceId = (PCHAR)&(newBMListPtr->DeviceIdStr); + newBMListPtr->DeviceIdLength = 4; - newBMListPtr->RaidFlags = RaidFlags; + newBMListPtr->RaidFlags = RaidFlags; // } - newBMListPtr->slotNumber = slotData.u.AsULONG; - newBMListPtr->MasterDev = IsMasterDev(&pciData) ? 1 : 0; - newBMListPtr->busNumber = busNumber; + newBMListPtr->slotNumber = slotData.u.AsULONG; + newBMListPtr->MasterDev = IsMasterDev(&pciData) ? 1 : 0; + newBMListPtr->busNumber = busNumber; - newBMListPtr->NeedAltInit = NeedPciAltInit; - newBMListPtr->Known = known; + newBMListPtr->NeedAltInit = NeedPciAltInit; + newBMListPtr->Known = known; - KdPrint2((PRINT_PREFIX "Add to BMList, AltInit %d\n", NeedPciAltInit)); - } else { - KdPrint2((PRINT_PREFIX "count: BMListLen++\n")); - } - - BMListLen++; + KdPrint2((PRINT_PREFIX "Add to BMList, AltInit %d\n", NeedPciAltInit)); + } else { + KdPrint2((PRINT_PREFIX "count: BMListLen++\n")); + PciDevMap[busNumber*PCI_MAX_DEVICES + slotNumber] |= (1 << funcNumber); } + + BMListLen++; + } } } @@ -650,10 +674,14 @@ BMListLen=0; } } +exit: KdPrint2((PRINT_PREFIX " BMListLen=%x\n", BMListLen)); if(deviceExtension) { ExFreePool(deviceExtension); } + if(PciDevMap) { + ExFreePool(PciDevMap); + } return(SP_RETURN_NOT_FOUND); } // end UniataEnumBusMasterController__() @@ -1642,7 +1670,7 @@ chan->RegTranslation[IDX_SATA_IO].MemIo ? "mem" : "io")); if(!(deviceExtension->HwFlags & UNIATA_AHCI)) { -#if DBG +#ifdef _DEBUG UniataDumpATARegs(chan); #endif @@ -2302,11 +2330,14 @@ BaseIoAddress2 = (PIDE_REGISTERS_2)ioSpace; KdPrint2((PRINT_PREFIX " BaseIoAddress1=%x\n", BaseIoAddress1)); KdPrint2((PRINT_PREFIX " BaseIoAddress2=%x\n", BaseIoAddress2)); + if(!irq) { + KdPrint2((PRINT_PREFIX " expected InterruptLevel=%x\n", InterruptLevels[*adapterCount - 1])); + } UniataInitMapBase(chan, BaseIoAddress1, BaseIoAddress2); UniataInitMapBM(deviceExtension, 0, FALSE); -#if DBG +#ifdef _DEBUG UniataDumpATARegs(chan); #endif @@ -2655,6 +2686,14 @@ if(deviceExtension->HwFlags & UNIATA_AHCI) { KdPrint2((PRINT_PREFIX " AHCI HDD at home\n")); return ATA_AT_HOME_HDD; + } + if(g_opt_VirtualMachine == VM_BOCHS) { + GetStatus(chan, signatureLow); + if(!signatureLow) { + KdPrint2((PRINT_PREFIX " 0-status BOCHS - not present\n")); + UniataForgetDevice(LunExt); + return ATA_AT_HOME_NOBODY; + } } AtapiStallExecution(10); diff -ruN v45h4\driver\id_sata.cpp v45h9\driver\id_sata.cpp --- v45h4\driver\id_sata.cpp Mon Apr 06 16:26:54 2015 +++ v45h9\driver\id_sata.cpp Wed Sep 23 18:18:12 2015 @@ -2317,13 +2317,13 @@ KdPrint2((" Incomplete command, CI %#x, ACT %#x\n", CI, ACT)); KdPrint2((" FIS status %#x, error %#x\n", RCV_FIS[2], RCV_FIS[3])); -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif if(!UniataAhciAbortOperation(chan)) { KdPrint2((" Abort failed, need RESET\n")); } -#if DBG +#ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif chan->AhciPrevCI = CI & ~((ULONG)1 << tag); diff -ruN v45h4\driver\id_sata.h v45h9\driver\id_sata.h --- v45h4\driver\id_sata.h Wed Aug 13 21:52:56 2014 +++ v45h9\driver\id_sata.h Wed Sep 23 18:18:02 2015 @@ -123,7 +123,7 @@ IN PVOID HwDeviceExtension ); -#if DBG +#ifdef _DEBUG VOID NTAPI UniataDumpAhciPortRegs( diff -ruN v45h4\driver\inc\misc.h v45h9\driver\inc\misc.h --- v45h4\driver\inc\misc.h Mon Aug 06 21:50:04 2012 +++ v45h9\driver\inc\misc.h Wed Sep 23 18:17:36 2015 @@ -5,7 +5,7 @@ /* The definitions look so crappy, because the code doesn't care whether the source is an array or an integer */ -#define MOV_DD_SWP(a,b) ((a) = RtlUlongByteSwap(*(PULONG)&(b))) +#define MOV_DD_SWP(a,b) ( ((PULONG)&(a))[0] = RtlUlongByteSwap(*(PULONG)&(b))) #define MOV_DW_SWP(a,b) ( ((PUSHORT)&(a))[0] = RtlUshortByteSwap(*(PUSHORT)&(b))) #define MOV_SWP_DW2DD(a,b) ((a) = RtlUshortByteSwap(*(PUSHORT)&(b))) #define MOV_QD_SWP(a,b) { ((PULONG)&(a))[0] = RtlUlongByteSwap( ((PULONG)&(b))[1]); ((PULONG)&(a))[1] = RtlUlongByteSwap( ((PULONG)&(b))[0]); } diff -ruN v45h4\driver\srb.h v45h9\driver\srb.h --- v45h4\driver\srb.h Sun Mar 20 01:37:04 2011 +++ v45h9\driver\srb.h Wed Sep 23 19:06:22 2015 @@ -14,6 +14,8 @@ #ifndef _NTSRB_ #define _NTSRB_ +#pragma pack(push, 8) + // Define SCSI maximum configuration parameters. #define SCSI_MAXIMUM_LOGICAL_UNITS 8 @@ -970,5 +972,7 @@ // end_ntminitape #endif //USER_MODE + +#pragma pack(pop) #endif // diff -ruN v45h4\driver\tools.h v45h9\driver\tools.h --- v45h4\driver\tools.h Fri Jul 20 19:29:14 2012 +++ v45h9\driver\tools.h Wed Sep 23 19:05:50 2015 @@ -34,6 +34,8 @@ #ifndef __TOOLS_H__ #define __TOOLS_H__ +#pragma pack(push, 1) + #ifdef __cplusplus extern "C" { #endif //__cplusplus @@ -182,5 +184,7 @@ #ifndef offsetof #define offsetof(type, field) (ULONG)&(((type *)0)->field) #endif //offsetof + +#pragma pack(pop) #endif // __TOOLS_H__ diff -ruN v45h4\driver\uniata_ver.h v45h9\driver\uniata_ver.h --- v45h4\driver\uniata_ver.h Mon Apr 06 17:37:10 2015 +++ v45h9\driver\uniata_ver.h Wed Sep 23 19:35:32 2015 @@ -1,10 +1,10 @@ -#define UNIATA_VER_STR "45h4" -#define UNIATA_VER_DOT 0.45.8.4 +#define UNIATA_VER_STR "45h9" +#define UNIATA_VER_DOT 0.45.8.9 #define UNIATA_VER_MJ 0 #define UNIATA_VER_MN 45 #define UNIATA_VER_SUB_MJ 8 -#define UNIATA_VER_SUB_MN 4 -#define UNIATA_VER_DOT_COMMA 0,45,8,4 -#define UNIATA_VER_DOT_STR "0.45.8.4" +#define UNIATA_VER_SUB_MN 9 +#define UNIATA_VER_DOT_COMMA 0,45,8,9 +#define UNIATA_VER_DOT_STR "0.45.8.9" #define UNIATA_VER_YEAR 2015 #define UNIATA_VER_YEAR_STR "2015"