=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2019.11.14 15:30:14 =~=~=~=~=~=~=~=~=~=~=~= (../boot/freeldr/freeldr/disk/partition.c:420) fixme: DiskGetPartitionEntry() unimplemented for GPT (../boot/freeldr/freeldr/disk/partition.c:420) fixme: DiskGetPartitionEntry() unimplemented for GPT (../boot/freeldr/freeldr/arch/i386/machpc.c:220) err: PnP-BIOS failed to enumerate device nodes (ntoskrnl/kd/kdio.c:105) ----------------------------------------------------- (ntoskrnl/kd/kdio.c:106) ReactOS 0.4.14-dev (Build 20191114-0.4.14-dev-317-g96040ec) (Commit 96040ecff93aa533a64e73ac9aeb568196082959) (ntoskrnl/kd/kdio.c:107) 1 System Processor [3512 MB Memory] (ntoskrnl/kd/kdio.c:108) Command Line: DEBUG DEBUGPORT=COM1 BAUDRATE=115200 SOS MININT RDPATH=LIVECD.ISO RDEXPORTASCD (ntoskrnl/kd/kdio.c:109) ARC Paths: ramdisk(0) \ ramdisk(0) \reactos\ (ntoskrnl/ke/i386/cpu.c:450) Supported CPU features : KF_V86_VIS KF_RDTSC KF_CR4 KF_CMOV KF_GLOBAL_PAGE KF_LARGE_PAGE KF_MTRR KF_CMPXCHG8B KF_MMX KF_WORKING_PTE KF_PAT KF_FXSR KF_FAST_SYSCALL KF_XMMI KF_XMMI64 KF_NX_BIT (ntoskrnl/ke/i386/cpu.c:722) Prefetch Cache: 64 bytes L2 Cache: 524288 bytes L2 Cache Line: 64 bytes L2 Cache Associativity: 8 (ntoskrnl/mm/ARM3/mminit.c:1452) HAL I/O Mapping at FFFE0000 is unsafe (ntoskrnl/mm/mminit.c:131) 0x80000000 - 0x98000000 Boot Loaded Image (ntoskrnl/mm/mminit.c:135) 0xB0000000 - 0xB182D000 PFN Database (ntoskrnl/mm/mminit.c:139) 0xB182D000 - 0xB7E4D000 ARM3 Non Paged Pool (ntoskrnl/mm/mminit.c:143) 0xB9400000 - 0xBB400000 System View Space (ntoskrnl/mm/mminit.c:147) 0xBB400000 - 0xC0000000 Session Space (ntoskrnl/mm/mminit.c:150) 0xC0000000 - 0xC03FFFFF Page Tables (ntoskrnl/mm/mminit.c:153) 0xC0300000 - 0xC0300FFF Page Directories (ntoskrnl/mm/mminit.c:156) 0xC0400000 - 0xC07FFFFF Hyperspace (ntoskrnl/mm/mminit.c:159) 0xC1000000 - 0xE0FFFFFF System Cache (ntoskrnl/mm/mminit.c:163) 0xE1000000 - 0xECC00000 ARM3 Paged Pool (ntoskrnl/mm/mminit.c:166) 0xECC00000 - 0xF7BE0000 System PTE Space (ntoskrnl/mm/mminit.c:169) 0xF7BE0000 - 0xFFBE0000 Non Paged Pool Expansion PTE Space (ntoskrnl/mm/ARM3/sysldr.c:2467) Skipping NT 4 driver @ 80800000 (ntoskrnl/config/cmcheck.c:25) CmCheckRegistry(0xB7B9D008, 2) is UNIMPLEMENTED! (hal/halx86/legacy/bussupp.c:699) Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail! (hal/halx86/legacy/bussupp.c:728) Found parent bus (indicating PCI Bridge). PCI devices may fail! ====== PCI BUS HARDWARE DETECTION ======= 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] (rev 00) Subsystem: Unknown [1043:8747] Flags: fast devsel, latency 0 00:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) I/O Memory Management Unit [1022:1451] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0 Memory at 00010100 (32-bit, non-prefetchable) [size=256] I/O ports at 01f0 [size=16] Memory at f7b0f7b0 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 00:01.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0 Memory at 00070200 (32-bit, non-prefetchable) [size=512] I/O ports at 2000f1f0 [size=16] Memory at f760f720 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:03.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0 Memory at 00080800 (32-bit, non-prefetchable) [size=2K] I/O ports at 2000e1e0 [size=32] Memory at f700f600 (32-bit, non-prefetchable) [size=512] I/O ports at f1f1e000 [size=8K] 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ assignment required Memory at 00090900 (32-bit, non-prefetchable) [size=256] I/O ports at 01f0 [size=16] Memory at f790f770 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ assignment required Memory at 000a0a00 (32-bit, non-prefetchable) [size=512] I/O ports at 01f0 [size=16] Memory at f7a0f7a0 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 59) Subsystem: Unknown [1043:8747] Flags: 66MHz, medium devsel, latency 0 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51) Subsystem: Unknown [1043:8747] Flags: bus master, 66MHz, medium devsel, latency 0 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0 [1022:1460] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1 [1022:1461] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2 [1022:1462] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3 [1022:1463] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4 [1022:1464] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5 [1022:1465] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6 [1022:1466] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7 [1022:1467] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 01:00.0 Non-Volatile memory controller [0108]: Silicon Motion, Inc. Unknown device [126f:2262] (rev 03) Subsystem: Unknown [126f:2262] Flags: bus master, fast devsel, latency 0, IRQ 11 Memory at f7b00000 (64-bit, non-prefetchable) [size=1M] Device is using IRQ 11! ISA Cards using that IRQ may fail! 02:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Unknown device [1022:57ad] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at 00070300 (64-bit, non-prefetchable) [size=256] I/O ports at f1f0 [size=16] Memory at f760f720 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 03:05.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Unknown device [1022:57a3] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0 I/O ports at 40400 [size=1K] I/O ports at f1f0 [size=16] Memory at f760f760 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 03:08.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Unknown device [1022:57a4] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 10 I/O ports at 50500 [size=256] I/O ports at 01f0 [size=16] Memory at f730f720 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 03:09.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Unknown device [1022:57a4] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 15 I/O ports at 60600 [size=512] I/O ports at 01f0 [size=16] Memory at f750f750 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 03:0a.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Unknown device [1022:57a4] (rev 00) Subsystem: Unknown [0000:0000] Flags: bus master, fast devsel, latency 0, IRQ 05 I/O ports at 70700 [size=256] I/O ports at 01f0 [size=16] Memory at f740f740 (32-bit, non-prefetchable) [size=256] I/O ports at 1fff0 [size=16] 04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 26) Subsystem: Unknown [1043:87c3] Flags: bus master, fast devsel, latency 0, IRQ 15 I/O ports at f000 [size=4K] Memory at f7604000 (64-bit, non-prefetchable) [size=16K] Memory at f7600000 (64-bit, non-prefetchable) [size=2M] Device is using IRQ 15! ISA Cards using that IRQ may fail! 05:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 05:00.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at f7300000 (64-bit, non-prefetchable) [size=1M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 05:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c] (rev 00) Subsystem: Unknown [1022:148c] Flags: bus master, fast devsel, latency 0, IRQ 05 Memory at f7200000 (64-bit, non-prefetchable) [size=2M] Device is using IRQ 5! ISA Cards using that IRQ may fail! 06:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) Subsystem: Unknown [1022:7901] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at f7500000 (32-bit, non-prefetchable) [size=1M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 07:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) Subsystem: Unknown [1022:7901] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at f7400000 (32-bit, non-prefetchable) [size=4M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 08:00.0 VGA compatible controller [0300]: NVIDIA Corporation GP106 [GeForce GTX 1060 6GB] [10de:1c03] (rev a1) Subsystem: Unknown [1043:85ab] Flags: bus master, fast devsel, latency 0, IRQ 05 Memory at f6000000 (32-bit, non-prefetchable) [size=32M] Memory at e0000000 (64-bit, prefetchable) [size=512M] Memory at f0000000 (64-bit, prefetchable) [size=256M] I/O ports at e000 [size=8K] Device is using IRQ 5! ISA Cards using that IRQ may fail! 08:00.1 Audio device [0403]: NVIDIA Corporation GP106 High Definition Audio Controller [10de:10f1] (rev a1) Subsystem: Unknown [1043:85ab] Flags: bus master, fast devsel, latency 0, IRQ 14 Memory at f7080000 (32-bit, non-prefetchable) [size=512K] Device is using IRQ 14! ISA Cards using that IRQ may fail! 09:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 09:00.2 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at f7800000 (32-bit, non-prefetchable) [size=8M] Memory at f7900000 (32-bit, non-prefetchable) [size=1M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 09:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:145f] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 15 Memory at f7700000 (64-bit, non-prefetchable) [size=1M] Device is using IRQ 15! ISA Cards using that IRQ may fail! 0a:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 0a:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 11 Memory at f7a08000 (32-bit, non-prefetchable) [size=32K] Device is using IRQ 11! ISA Cards using that IRQ may fail! 0a:00.3 Audio device [0403]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) HD Audio Controller [1022:1457] (rev 00) Subsystem: Unknown [1043:8797] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at f7a00000 (32-bit, non-prefetchable) [size=2M] Device is using IRQ 10! ISA Cards using that IRQ may fail! ====== PCI BUS DETECTION COMPLETE ======= PC Compatible Eisa/Isa HAL Detected (sdk/lib/rtl/image.c:172) Invalid base address: 00000000 (ntoskrnl/io/iomgr/driver.c:1635) '\Driver\SACDRV' initialization failed, status (0xc0000037) (ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\SACDRV' ATAPI IDE MiniPort Driver (UniATA) v 0.47a HwInitializationDataSize = 50 UniATA: parse ArgumentString (drivers/storage/scsiport/scsiport.c:5859) ZwOpenKey() failed with Status=0xC0000034 Parameter PrintLogo Parameter PrintLogo = 0x0 Parameter IgnoreIsaCompatiblePci Parameter IgnoreIsaCompatiblePci = 0x0 Parameter IgnoreNativePci Parameter IgnoreNativePci = 0x0 UniATA Init: OS should be ReactOS UniATA Init: OS ver 4.1 (1), 1 CPU(s) Performance calibration: dt=14995, counter=3747707 InitBadBlocks general InitBadBlocks returned: 0xc0000034 Parameter SkipRaids Parameter SkipRaids = 0x1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 Parameter LogToDisplay Parameter LogToDisplay = 0x0 set NeedPhysicalAddresses = TRUE set AtapiAdapterControl() ptr UniATA init... (0) Parameter VirtualMachineType Parameter VirtualMachineType = 0x0 Parameter VirtualBox Parameter VirtualBox = 0x0 ATAPI IDE enum supported PCI BusMaster Devices UniataEnumBusMasterController__: maxPciBus=16 pass 0 DevId = 14501022 Class = 0006/0000, SubVen/Sys 1043/8747 DevId = 14511022 Class = 0008/0006, SubVen/Sys 1043/8747 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14531022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14531022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14531022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14541022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14541022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 790B1022 Class = 000C/0005, SubVen/Sys 1043/8747 DevId = 790E1022 Class = 0006/0001, SubVen/Sys 1043/8747 DevId = 14601022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14611022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14621022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14631022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14641022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14651022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14661022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14671022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 2262126F Class = 0001/0008, SubVen/Sys 126f/2262 -- BusID: 0x1:0x0:0x0 Storage Class DevId = 2262126F Class = 0001/0008, ProgIf 02 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Subclass not supported Subclass not supported DevId = 57AD1022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A31022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A41022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A41022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A41022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 816810EC Class = 0002/0000, SubVen/Sys 1043/87c3 DevId = 14851022 Class = 0013/0000, SubVen/Sys 1043/8747 DevId = 149C1022 Class = 000C/0003, SubVen/Sys 1043/8747 DevId = 149C1022 Class = 000C/0003, SubVen/Sys 1022/148c DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x6:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 0 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xf7500000 count: BMListLen++ DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x7:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 0 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xf7400000 count: BMListLen++ DevId = 1C0310DE Class = 0003/0000, SubVen/Sys 1043/85ab DevId = 10F110DE Class = 0004/0003, SubVen/Sys 1043/85ab DevId = 145A1022 Class = 0013/0000, SubVen/Sys 1043/8747 DevId = 14561022 Class = 0010/0080, SubVen/Sys 1043/8747 DevId = 145F1022 Class = 000C/0003, SubVen/Sys 1043/8747 DevId = 14551022 Class = 0013/0000, SubVen/Sys 1043/8747 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1043/8747 -- BusID: 0xa:0x0:0x2 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 0 InterruptPin = 0x2 InterruptLine = 0xb Range 5 = 0xf7a08000 count: BMListLen++ DevId = 14571022 Class = 0004/0003, SubVen/Sys 1043/8797 pass 1 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x6:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 1 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xf7500000 found suitable device DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x7:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 1 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xf7400000 found suitable device DevId = 79011022 Class = 0001/0006, SubVen/Sys 1043/8747 -- BusID: 0xa:0x0:0x2 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 1 InterruptPin = 0x2 InterruptLine = 0xb Range 5 = 0xf7a08000 found suitable device pass 2 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x6:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 2 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xf7500000 found suitable device Add to BMList, AltInit 0 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x7:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 2 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xf7400000 found suitable device Add to BMList, AltInit 0 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1043/8747 -- BusID: 0xa:0x0:0x2 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 2 InterruptPin = 0x2 InterruptLine = 0xb Range 5 = 0xf7a08000 found suitable device Add to BMList, AltInit 0 BMListLen=3 Parameter WaitBusyCount Parameter WaitBusyCount = 0xc8 Parameter WaitBusyDelay Parameter WaitBusyDelay = 0xa Parameter WaitDrqDelay Parameter WaitDrqDelay = 0xa Parameter WaitBusyLongCount Parameter WaitBusyLongCount = 0x7d0 Parameter WaitBusyLongDelay Parameter WaitBusyLongDelay = 0xfa Parameter AtapiSendDisableIntr Parameter AtapiSendDisableIntr = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiNoDma Parameter AtapiNoDma = 0x0 Parameter MaxIsrWait Parameter MaxIsrWait = 0x28 Parameter DriveSelectNanoDelay Parameter DriveSelectNanoDelay = 0x0 ATAPI IDE: Look for legacy ISA-bridged PCI IDE controller (onboard) ATAPI IDE: BMListLen 3 !BMList[i].MasterDev ATAPI IDE: Look for PCI IDE controller ATAPI IDE: i 0, BMListLen 3 Try init 1022 7901 (hal/halx86/legacy/bussupp.c:1274) Slot assignment for 5 on bus 6 (hal/halx86/legacy/bus/pcibus.c:742) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=0, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0x6 slotNumber=0x0 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf7740000 MemIo AHCI Base: 0xf7740000 MemIo 1 Proc 0 AHCI_0x0 (0xf7740000) = 0xf737ff01 AHCI_0x4 (0xf7740004) = 0x80000000 AHCI_0x8 (0xf7740008) = 0x0 AHCI_0xc (0xf774000c) = 0xc AHCI_0x10 (0xf7740010) = 0x10301 check AHCI mode, GHC 0x80000000 AHCI CAP 0xf737ff01, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0xc Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0xc Force PortMask 0xc CommandSlots 31 Detected Channels 4 / 4 Adjusted Channels 4 AHCI version 1.31 controller with 4 ports (mask 0xc) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf7740000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 PortMask 0xf Parameter PortMask Parameter PortMask = 0xf Force PortMask 0xf mask -> 4 chans Parameter NumberChannels Parameter NumberChannels = 0x4 reg -> 4 chans Final PortMask 0xf allocate 2 Luns for 4 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb7b982b4 AtapiReadChipConfig: dev 0x0, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x0, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf7740000 MemIo 1 Proc 0 AHCI_0x0 (0xf7740000) = 0xf737ff01 AHCI_0x4 (0xf7740004) = 0x80000000 AHCI_0x8 (0xf7740008) = 0x0 AHCI_0xc (0xf774000c) = 0xc AHCI_0x10 (0xf7740010) = 0x10301 get GHC disable intr, GHC 0x80000000 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff01 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0xc AHCI PI mask 0xf masked AHCI PI 0xc SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb7e01008 Lun 0x0 Lun ptr 0xb7b96000 Lun 0x1 Lun ptr 0xb7b96318 AtaReq 0xb7e02000: cmd aligned b7e02080, d=20 ahci_cmd_ptr 0xb7e02080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b94000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b94000 AtapiVirtToPhysAddr_: b7b94000 -> 00000000:1e272000 AtapiDmaAlloc: CLP Phys BASE 1e272000 imp: 0xc & 0x1 chan 0 not implemented chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb7e01268 Lun 0x0 Lun ptr 0xb7b96630 Lun 0x1 Lun ptr 0xb7b96948 AtaReq 0xb7e03000: cmd aligned b7e03080, d=20 ahci_cmd_ptr 0xb7e03080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7dff000 AtapiDmaAlloc: CLP BASE 1k-aligned b7dff000 AtapiVirtToPhysAddr_: b7dff000 -> 00000000:1e4dd000 AtapiDmaAlloc: CLP Phys BASE 1e4dd000 imp: 0xc & 0x2 chan 1 not implemented chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb7e014c8 Lun 0x0 Lun ptr 0xb7b96c60 Lun 0x1 Lun ptr 0xb7b96f78 AtaReq 0xb7e04000: cmd aligned b7e04080, d=20 ahci_cmd_ptr 0xb7e04080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b92000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b92000 AtapiVirtToPhysAddr_: b7b92000 -> 00000000:1e270000 AtapiDmaAlloc: CLP Phys BASE 1e270000 imp: 0xc & 0x4 UniataAhciResume: lChan 2 WriteChannelPort4 0 => ch2[14] AHCI CLB setup WriteChannelPort4 1e270000 => ch2[0] WriteChannelPort4 0 => ch2[4] AHCI RCV FIS setup WriteChannelPort4 1e270400 => ch2[8] WriteChannelPort4 0 => ch2[c] WriteChannelPort4 10000006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 400040 WriteChannelPort4 400040 => ch2[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x400040 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x40c017 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x0 AHCI2_0x30 (0xf7740230) = 0x4050000 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb7e01728 Lun 0x0 Lun ptr 0xb7b97290 Lun 0x1 Lun ptr 0xb7b975a8 AtaReq 0xb7e05000: cmd aligned b7e05080, d=20 ahci_cmd_ptr 0xb7e05080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7dfd000 AtapiDmaAlloc: CLP BASE 1k-aligned b7dfd000 AtapiVirtToPhysAddr_: b7dfd000 -> 00000000:1e4db000 AtapiDmaAlloc: CLP Phys BASE 1e4db000 imp: 0xc & 0x8 UniataAhciResume: lChan 3 WriteChannelPort4 0 => ch3[14] AHCI CLB setup WriteChannelPort4 1e4db000 => ch3[0] WriteChannelPort4 0 => ch3[4] AHCI RCV FIS setup WriteChannelPort4 1e4db400 => ch3[8] WriteChannelPort4 0 => ch3[c] WriteChannelPort4 10000006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 400040 WriteChannelPort4 400040 => ch3[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 AHCI port 3 Base: 0xf7740280 MemIo 1 Proc 0 AHCI3_0x0 (0xf7740280) = 0x1e4db000 AHCI3_0x4 (0xf7740284) = 0x0 AHCI3_0x8 (0xf7740288) = 0x1e4db400 AHCI3_0xc (0xf774028c) = 0x0 AHCI3_0x10 (0xf7740290) = 0x400040 AHCI3_0x14 (0xf7740294) = 0x0 AHCI3_0x18 (0xf7740298) = 0x40c017 AHCI3_0x1c (0xf774029c) = 0x0 AHCI3_0x20 (0xf77402a0) = 0x150 AHCI3_0x24 (0xf77402a4) = 0x101 AHCI3_0x28 (0xf77402a8) = 0x123 AHCI3_0x2c (0xf77402ac) = 0x0 AHCI3_0x30 (0xf77402b0) = 0x4050000 AHCI3_0x34 (0xf77402b4) = 0x0 AHCI3_0x38 (0xf77402b8) = 0x0 AHCI3_0x3c (0xf77402bc) = 0x0 simplexOnly = 0 (2)!MasterDev update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 10, Level2 0, Vector 10, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x4, channel 0x0 de 0xb7b982b4, Channel 0x0 chan = 0xb7e01008 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb7e01008 Lun 0x0 Lun ptr 0xb7b96000 Lun 0x1 Lun ptr 0xb7b96318 AtaReq 0xb7e02000: cmd aligned b7e02080, d=20 ahci_cmd_ptr 0xb7e02080 AtapiReadChipConfig: devExt 0xb7b982b4 AtapiReadChipConfig: dev 0x0, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf7740120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf7740128), Mem: AtapiDmaAlloc: AHCI already initialized b7b94000 de 0xb7b982b4, Channel 0x1 chan = 0xb7e01268 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb7e01268 Lun 0x0 Lun ptr 0xb7b96630 Lun 0x1 Lun ptr 0xb7b96948 AtaReq 0xb7e03000: cmd aligned b7e03080, d=20 ahci_cmd_ptr 0xb7e03080 AtapiReadChipConfig: devExt 0xb7b982b4 AtapiReadChipConfig: dev 0x0, ph chan 1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf77401a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf77401a8), Mem: AtapiDmaAlloc: AHCI already initialized b7dff000 de 0xb7b982b4, Channel 0x2 chan = 0xb7e014c8 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb7e014c8 Lun 0x0 Lun ptr 0xb7b96c60 Lun 0x1 Lun ptr 0xb7b96f78 AtaReq 0xb7e04000: cmd aligned b7e04080, d=20 ahci_cmd_ptr 0xb7e04080 AtapiReadChipConfig: devExt 0xb7b982b4 AtapiReadChipConfig: dev 0x0, ph chan 2 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf7740220), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf7740228), Mem: AtapiDmaAlloc: AHCI already initialized b7b92000 de 0xb7b982b4, Channel 0x3 chan = 0xb7e01728 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb7e01728 Lun 0x0 Lun ptr 0xb7b97290 Lun 0x1 Lun ptr 0xb7b975a8 AtaReq 0xb7e05000: cmd aligned b7e05080, d=20 ahci_cmd_ptr 0xb7e05080 AtapiReadChipConfig: devExt 0xb7b982b4 AtapiReadChipConfig: dev 0x0, ph chan 3 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf77402a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf77402a8), Mem: AtapiDmaAlloc: AHCI already initialized b7dfd000 exit: init spinlock MasterDev=0x0, NumberChannels=0x4, Isr2DevObj=0x0 Init ISR: Multichannel native mode, go... Create DO DO name: len(38, 38), \Device\uniata0_2ch HalGetInterruptVector OrigAdapterInterfaceType=5 SystemIoBusNumber=6 BusInterruptLevel=10 BusInterruptVector=10 isr2_de 0xb7e01ed8 isr2_vector 0x3a isr2_irql 0x11 isr2_affinity 0x1 IoConnectInterrupt MasterDev=0x0, NumberChannels=0x4, Isr2DevObj=0xb7e01e20 final chan[4] InterruptMode: 0, Level 10, Level2 0, Vector 10, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf7740000 MemIo 1 Proc 0 AHCI_0x0 (0xf7740000) = 0xf737ff01 AHCI_0x4 (0xf7740004) = 0x80000002 AHCI_0x8 (0xf7740008) = 0x0 AHCI_0xc (0xf774000c) = 0xc AHCI_0x10 (0xf7740010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff01 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0xc AHCI PI mask 0xf masked AHCI PI 0xc SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb7e01008 Lun 0x0 Lun ptr 0xb7b96000 Lun 0x1 Lun ptr 0xb7b96318 AtaReq 0xb7e02000: cmd aligned b7e02080, d=20 ahci_cmd_ptr 0xb7e02080 AtapiDmaAlloc: AHCI already initialized b7b94000 imp: 0xc & 0x1 chan 0 not implemented chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb7e01268 Lun 0x0 Lun ptr 0xb7b96630 Lun 0x1 Lun ptr 0xb7b96948 AtaReq 0xb7e03000: cmd aligned b7e03080, d=20 ahci_cmd_ptr 0xb7e03080 AtapiDmaAlloc: AHCI already initialized b7dff000 imp: 0xc & 0x2 chan 1 not implemented chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb7e014c8 Lun 0x0 Lun ptr 0xb7b96c60 Lun 0x1 Lun ptr 0xb7b96f78 AtaReq 0xb7e04000: cmd aligned b7e04080, d=20 ahci_cmd_ptr 0xb7e04080 AtapiDmaAlloc: AHCI already initialized b7b92000 imp: 0xc & 0x4 UniataAhciResume: lChan 2 WriteChannelPort4 0 => ch2[14] AHCI CLB setup WriteChannelPort4 1e270000 => ch2[0] WriteChannelPort4 0 => ch2[4] AHCI RCV FIS setup WriteChannelPort4 1e270400 => ch2[8] WriteChannelPort4 0 => ch2[c] WriteChannelPort4 10000006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 400040 WriteChannelPort4 400040 => ch2[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x400040 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x40c017 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x0 AHCI2_0x30 (0xf7740230) = 0x4050000 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb7e01728 Lun 0x0 Lun ptr 0xb7b97290 Lun 0x1 Lun ptr 0xb7b975a8 AtaReq 0xb7e05000: cmd aligned b7e05080, d=20 ahci_cmd_ptr 0xb7e05080 AtapiDmaAlloc: AHCI already initialized b7dfd000 imp: 0xc & 0x8 UniataAhciResume: lChan 3 WriteChannelPort4 0 => ch3[14] AHCI CLB setup WriteChannelPort4 1e4db000 => ch3[0] WriteChannelPort4 0 => ch3[4] AHCI RCV FIS setup WriteChannelPort4 1e4db400 => ch3[8] WriteChannelPort4 0 => ch3[c] WriteChannelPort4 10000006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 400040 WriteChannelPort4 400040 => ch3[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 AHCI port 3 Base: 0xf7740280 MemIo 1 Proc 0 AHCI3_0x0 (0xf7740280) = 0x1e4db000 AHCI3_0x4 (0xf7740284) = 0x0 AHCI3_0x8 (0xf7740288) = 0x1e4db400 AHCI3_0xc (0xf774028c) = 0x0 AHCI3_0x10 (0xf7740290) = 0x400040 AHCI3_0x14 (0xf7740294) = 0x0 AHCI3_0x18 (0xf7740298) = 0x40c017 AHCI3_0x1c (0xf774029c) = 0x0 AHCI3_0x20 (0xf77402a0) = 0x150 AHCI3_0x24 (0xf77402a4) = 0x101 AHCI3_0x28 (0xf77402a8) = 0x123 AHCI3_0x2c (0xf77402ac) = 0x0 AHCI3_0x30 (0xf77402b0) = 0x4050000 AHCI3_0x34 (0xf77402b4) = 0x0 AHCI3_0x38 (0xf77402b8) = 0x0 AHCI3_0x3c (0xf77402bc) = 0x0 imp: 0xc & 0x1 imp: 0xc & 0x2 imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 0 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x0, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf7740280 MemIo 1 Proc 0 AHCI3_0x0 (0xf7740280) = 0x1e4db000 AHCI3_0x4 (0xf7740284) = 0x0 AHCI3_0x8 (0xf7740288) = 0x1e4db400 AHCI3_0xc (0xf774028c) = 0x0 AHCI3_0x10 (0xf7740290) = 0x0 AHCI3_0x14 (0xf7740294) = 0x0 AHCI3_0x18 (0xf7740298) = 0x404016 AHCI3_0x1c (0xf774029c) = 0x0 AHCI3_0x20 (0xf77402a0) = 0x150 AHCI3_0x24 (0xf77402a4) = 0x101 AHCI3_0x28 (0xf77402a8) = 0x123 AHCI3_0x2c (0xf77402ac) = 0x300 AHCI3_0x30 (0xf77402b0) = 0x0 AHCI3_0x34 (0xf77402b4) = 0x0 AHCI3_0x38 (0xf77402b8) = 0x0 AHCI3_0x3c (0xf77402bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 0 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7b982f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7e05080) AtapiVirtToPhysAddr_: b7e05080 -> 00000000:1e4e3080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x1, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 0/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b97290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 1 CI 0x1 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7b98978, AtaReq 0xb7e05000, CMD 0xb7e05080 ph 1e4e3080 AHCI setup FIS b7e05080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7e05000 AHCI AtaReq CMD 0xb7e05080 (ph 0x1e4e3080) prd_length 0x0, flags 0x5, base 1e4e3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01008, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e01008, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01008, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e01008, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01268, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e01268, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01268, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01268, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e01268, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01268, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7dec000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f77b0230) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7dec000: cmd aligned b7dec080, d=20 ahci_cmd_ptr 0xb7dec080 AtapiDmaSetup: mode 0x47, data f773fe30, count 24, lCh 2, dev 0 get Phys(AHCI_CMD=b7dec080) AtapiVirtToPhysAddr_: b7dec080 -> 00000000:1e4ca080 get Phys(data[0]=f773fe30) AtapiVirtToPhysAddr_: f773fe30 -> 00000000:1e276e30 set TERM ph data[0]=0:1e276e30 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7dec080, ch 2, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f77b0230 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch2[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7dec000 AHCI AtaReq CMD 0xb7dec080 (ph 0x1e4ca080) prd_length 0x1, flags 0xa5, base 1e4ca080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 AtapiStartIo: next Srb f77b0200 AtapiStartIo: query PORT for next request AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7e014c8, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xf77b0200, chan 0xb7e014c8 senseBuffer 0xb7ded000, chan 0xb7e014c8, ReqFlags 0xa AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7e014c8 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x1 AHCI2_0x14 (0xf7740214) = 0xfd4000ff AHCI2_0x18 (0xf7740218) = 0x140c017 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x50 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x1404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404006 => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 1400006 WriteChannelPort4 140000e => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 1400006 CMD 0x1400006 WriteChannelPort4 1400016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7e014c8 Lun 0x0 Lun ptr 0xb7b96c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 1404017 CMD 0x1404017 send CMD 0x404017, entries 0x1 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x404017 != 0x40c017) WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x4 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7e014c8 Lun 0x1 Lun ptr 0xb7b96f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x0, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7dec000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f77b0230) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7dec000: cmd aligned b7dec080, d=20 ahci_cmd_ptr 0xb7dec080 AtapiDmaSetup: mode 0x47, data f773fe30, count 24, lCh 2, dev 0 get Phys(AHCI_CMD=b7dec080) AtapiVirtToPhysAddr_: b7dec080 -> 00000000:1e4ca080 get Phys(data[0]=f773fe30) AtapiVirtToPhysAddr_: f773fe30 -> 00000000:1e276e30 set TERM ph data[0]=0:1e276e30 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7dec080, ch 2, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f77b0230 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch2[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7dec000 AHCI AtaReq CMD 0xb7dec080 (ph 0x1e4ca080) prd_length 0x1, flags 0xa5, base 1e4ca080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 AtapiStartIo: next Srb f77b0200 AtapiStartIo: query PORT for next request AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7e014c8, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xf77b0200, chan 0xb7e014c8 senseBuffer 0xb7ded000, chan 0xb7e014c8, ReqFlags 0xa AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7e014c8 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x1 AHCI2_0x14 (0xf7740214) = 0xfd4000ff AHCI2_0x18 (0xf7740218) = 0x140c017 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x50 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x1404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404006 => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 1400006 WriteChannelPort4 140000e => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 1400006 CMD 0x1400006 WriteChannelPort4 1400016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7e014c8 Lun 0x0 Lun ptr 0xb7b96c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 1404017 CMD 0x1404017 send CMD 0x404017, entries 0x1 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x404017 != 0x40c017) WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x4 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7e014c8 Lun 0x1 Lun ptr 0xb7b96f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x0, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7dec000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f77b0230) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7dec000: cmd aligned b7dec080, d=20 ahci_cmd_ptr 0xb7dec080 AtapiDmaSetup: mode 0x47, data f773fe30, count 24, lCh 2, dev 0 get Phys(AHCI_CMD=b7dec080) AtapiVirtToPhysAddr_: b7dec080 -> 00000000:1e4ca080 get Phys(data[0]=f773fe30) AtapiVirtToPhysAddr_: f773fe30 -> 00000000:1e276e30 set TERM ph data[0]=0:1e276e30 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7dec080, ch 2, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f77b0230 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch2[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7dec000 AHCI AtaReq CMD 0xb7dec080 (ph 0x1e4ca080) prd_length 0x1, flags 0xa5, base 1e4ca080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 AtapiStartIo: next Srb f77b0200 AtapiStartIo: query PORT for next request AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7e014c8, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xf77b0200, chan 0xb7e014c8 senseBuffer 0xb7ded000, chan 0xb7e014c8, ReqFlags 0xa AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7e014c8 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x1 AHCI2_0x14 (0xf7740214) = 0xfd4000ff AHCI2_0x18 (0xf7740218) = 0x140c017 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x50 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x1404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404006 => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 1400006 WriteChannelPort4 140000e => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 1400006 CMD 0x1400006 WriteChannelPort4 1400016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7e014c8 Lun 0x0 Lun ptr 0xb7b96c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 1404017 CMD 0x1404017 send CMD 0x404017, entries 0x1 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x404017 != 0x40c017) WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x4 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7e014c8 Lun 0x1 Lun ptr 0xb7b96f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf7740200 MemIo 1 Proc 0 AHCI2_0x0 (0xf7740200) = 0x1e270000 AHCI2_0x4 (0xf7740204) = 0x0 AHCI2_0x8 (0xf7740208) = 0x1e270400 AHCI2_0xc (0xf774020c) = 0x0 AHCI2_0x10 (0xf7740210) = 0x0 AHCI2_0x14 (0xf7740214) = 0x0 AHCI2_0x18 (0xf7740218) = 0x404016 AHCI2_0x1c (0xf774021c) = 0x0 AHCI2_0x20 (0xf7740220) = 0x100 AHCI2_0x24 (0xf7740224) = 0xeb140101 AHCI2_0x28 (0xf7740228) = 0x113 AHCI2_0x2c (0xf774022c) = 0x300 AHCI2_0x30 (0xf7740230) = 0x0 AHCI2_0x34 (0xf7740234) = 0x0 AHCI2_0x38 (0xf7740238) = 0x0 AHCI2_0x3c (0xf774023c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b982f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7b982f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7e04080) AtapiVirtToPhysAddr_: b7e04080 -> 00000000:1e4e2080 get Phys(data[0]=b7b982f8) AtapiVirtToPhysAddr_: b7b982f8 -> 00000000:1e2762f8 set TERM ph data[0]=0:1e2762f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x1, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7b96c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7b98938, AtaReq 0xb7e04000, CMD 0xb7e04080 ph 1e4e2080 AHCI setup FIS b7e04080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7e04000 AHCI AtaReq CMD 0xb7e04080 (ph 0x1e4e2080) prd_length 0x0, flags 0x5, base 1e4e2080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: Device 0x1 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e014c8, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e014c8, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e014c8, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7dec000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7dec000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x3:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7e01728, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e01728, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7dec000 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01728, f77b0200) AtapiStartIo: UniataRemoveRequest(b7e01728, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request (hal/halx86/legacy/bussupp.c:1274) Slot assignment for 5 on bus 10 (hal/halx86/legacy/bus/pcibus.c:742) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=0, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0xa slotNumber=0x0 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf773f000 MemIo AHCI Base: 0xf773f000 MemIo 1 Proc 0 AHCI_0x0 (0xf773f000) = 0xf737ff01 AHCI_0x4 (0xf773f004) = 0x80000002 AHCI_0x8 (0xf773f008) = 0x0 AHCI_0xc (0xf773f00c) = 0xc AHCI_0x10 (0xf773f010) = 0x10301 check AHCI mode, GHC 0x80000002 AHCI CAP 0xf737ff01, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0xc Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0xc Force PortMask 0xc CommandSlots 31 Detected Channels 4 / 4 Adjusted Channels 4 AHCI version 1.31 controller with 4 ports (mask 0xc) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf773f000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 PortMask 0xf Parameter PortMask Parameter PortMask = 0xf Force PortMask 0xf mask -> 4 chans Parameter NumberChannels Parameter NumberChannels = 0x4 reg -> 4 chans Final PortMask 0xf allocate 2 Luns for 4 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb7deb2b4 AtapiReadChipConfig: dev 0x0, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x0, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773f000 MemIo 1 Proc 0 AHCI_0x0 (0xf773f000) = 0xf737ff01 AHCI_0x4 (0xf773f004) = 0x80000002 AHCI_0x8 (0xf773f008) = 0x0 AHCI_0xc (0xf773f00c) = 0xc AHCI_0x10 (0xf773f010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff01 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0xc AHCI PI mask 0xf masked AHCI PI 0xc SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb7de8008 Lun 0x0 Lun ptr 0xb7de9000 Lun 0x1 Lun ptr 0xb7de9318 AtaReq 0xb7b8b000: cmd aligned b7b8b080, d=20 ahci_cmd_ptr 0xb7b8b080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b89000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b89000 AtapiVirtToPhysAddr_: b7b89000 -> 00000000:1e267000 AtapiDmaAlloc: CLP Phys BASE 1e267000 imp: 0xc & 0x1 chan 0 not implemented chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb7de8268 Lun 0x0 Lun ptr 0xb7de9630 Lun 0x1 Lun ptr 0xb7de9948 AtaReq 0xb7b8c000: cmd aligned b7b8c080, d=20 ahci_cmd_ptr 0xb7b8c080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b87000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b87000 AtapiVirtToPhysAddr_: b7b87000 -> 00000000:1e265000 AtapiDmaAlloc: CLP Phys BASE 1e265000 imp: 0xc & 0x2 chan 1 not implemented chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 Lun 0x1 Lun ptr 0xb7de9f78 AtaReq 0xb7b8d000: cmd aligned b7b8d080, d=20 ahci_cmd_ptr 0xb7b8d080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b85000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b85000 AtapiVirtToPhysAddr_: b7b85000 -> 00000000:1e263000 AtapiDmaAlloc: CLP Phys BASE 1e263000 imp: 0xc & 0x4 UniataAhciResume: lChan 2 WriteChannelPort4 0 => ch2[14] AHCI CLB setup WriteChannelPort4 1e263000 => ch2[0] WriteChannelPort4 0 => ch2[4] AHCI RCV FIS setup WriteChannelPort4 1e263400 => ch2[8] WriteChannelPort4 0 => ch2[c] WriteChannelPort4 10000006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 400040 WriteChannelPort4 400040 => ch2[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x400040 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x40c017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x0 AHCI2_0x30 (0xf773f230) = 0x4050000 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 Lun 0x1 Lun ptr 0xb7dea5a8 AtaReq 0xb7b8e000: cmd aligned b7b8e080, d=20 ahci_cmd_ptr 0xb7b8e080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b83000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b83000 AtapiVirtToPhysAddr_: b7b83000 -> 00000000:1e261000 AtapiDmaAlloc: CLP Phys BASE 1e261000 imp: 0xc & 0x8 UniataAhciResume: lChan 3 WriteChannelPort4 0 => ch3[14] AHCI CLB setup WriteChannelPort4 1e261000 => ch3[0] WriteChannelPort4 0 => ch3[4] AHCI RCV FIS setup WriteChannelPort4 1e261400 => ch3[8] WriteChannelPort4 0 => ch3[c] WriteChannelPort4 10000006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 400040 WriteChannelPort4 400040 => ch3[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x400040 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x40c017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x0 AHCI3_0x30 (0xf773f2b0) = 0x4050000 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 simplexOnly = 0 (2)!MasterDev patch irq line = 0xa update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 11, Level2 0, Vector 10, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x4, channel 0x0 de 0xb7deb2b4, Channel 0x0 chan = 0xb7de8008 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb7de8008 Lun 0x0 Lun ptr 0xb7de9000 Lun 0x1 Lun ptr 0xb7de9318 AtaReq 0xb7b8b000: cmd aligned b7b8b080, d=20 ahci_cmd_ptr 0xb7b8b080 AtapiReadChipConfig: devExt 0xb7deb2b4 AtapiReadChipConfig: dev 0x0, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773f120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773f128), Mem: AtapiDmaAlloc: AHCI already initialized b7b89000 de 0xb7deb2b4, Channel 0x1 chan = 0xb7de8268 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb7de8268 Lun 0x0 Lun ptr 0xb7de9630 Lun 0x1 Lun ptr 0xb7de9948 AtaReq 0xb7b8c000: cmd aligned b7b8c080, d=20 ahci_cmd_ptr 0xb7b8c080 AtapiReadChipConfig: devExt 0xb7deb2b4 AtapiReadChipConfig: dev 0x0, ph chan 1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773f1a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773f1a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b87000 de 0xb7deb2b4, Channel 0x2 chan = 0xb7de84c8 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 Lun 0x1 Lun ptr 0xb7de9f78 AtaReq 0xb7b8d000: cmd aligned b7b8d080, d=20 ahci_cmd_ptr 0xb7b8d080 AtapiReadChipConfig: devExt 0xb7deb2b4 AtapiReadChipConfig: dev 0x0, ph chan 2 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773f220), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773f228), Mem: AtapiDmaAlloc: AHCI already initialized b7b85000 de 0xb7deb2b4, Channel 0x3 chan = 0xb7de8728 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 Lun 0x1 Lun ptr 0xb7dea5a8 AtaReq 0xb7b8e000: cmd aligned b7b8e080, d=20 ahci_cmd_ptr 0xb7b8e080 AtapiReadChipConfig: devExt 0xb7deb2b4 AtapiReadChipConfig: dev 0x0, ph chan 3 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773f2a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773f2a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b83000 exit: init spinlock MasterDev=0x0, NumberChannels=0x4, Isr2DevObj=0xb7e01e20 Init ISR: Multichannel native mode, go... Already initialized [0] 0xb7e01e20 MasterDev=0x0, NumberChannels=0x4, Isr2DevObj=0xb7e01e20 final chan[4] InterruptMode: 0, Level 11, Level2 0, Vector 10, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773f000 MemIo 1 Proc 0 AHCI_0x0 (0xf773f000) = 0xf737ff01 AHCI_0x4 (0xf773f004) = 0x80000002 AHCI_0x8 (0xf773f008) = 0x0 AHCI_0xc (0xf773f00c) = 0xc AHCI_0x10 (0xf773f010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff01 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0xc AHCI PI mask 0xf masked AHCI PI 0xc SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb7de8008 Lun 0x0 Lun ptr 0xb7de9000 Lun 0x1 Lun ptr 0xb7de9318 AtaReq 0xb7b8b000: cmd aligned b7b8b080, d=20 ahci_cmd_ptr 0xb7b8b080 AtapiDmaAlloc: AHCI already initialized b7b89000 imp: 0xc & 0x1 chan 0 not implemented chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb7de8268 Lun 0x0 Lun ptr 0xb7de9630 Lun 0x1 Lun ptr 0xb7de9948 AtaReq 0xb7b8c000: cmd aligned b7b8c080, d=20 ahci_cmd_ptr 0xb7b8c080 AtapiDmaAlloc: AHCI already initialized b7b87000 imp: 0xc & 0x2 chan 1 not implemented chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 Lun 0x1 Lun ptr 0xb7de9f78 AtaReq 0xb7b8d000: cmd aligned b7b8d080, d=20 ahci_cmd_ptr 0xb7b8d080 AtapiDmaAlloc: AHCI already initialized b7b85000 imp: 0xc & 0x4 UniataAhciResume: lChan 2 WriteChannelPort4 0 => ch2[14] AHCI CLB setup WriteChannelPort4 1e263000 => ch2[0] WriteChannelPort4 0 => ch2[4] AHCI RCV FIS setup WriteChannelPort4 1e263400 => ch2[8] WriteChannelPort4 0 => ch2[c] WriteChannelPort4 10000006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 400040 WriteChannelPort4 400040 => ch2[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x400040 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x40c017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x0 AHCI2_0x30 (0xf773f230) = 0x4050000 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 Lun 0x1 Lun ptr 0xb7dea5a8 AtaReq 0xb7b8e000: cmd aligned b7b8e080, d=20 ahci_cmd_ptr 0xb7b8e080 AtapiDmaAlloc: AHCI already initialized b7b83000 imp: 0xc & 0x8 UniataAhciResume: lChan 3 WriteChannelPort4 0 => ch3[14] AHCI CLB setup WriteChannelPort4 1e261000 => ch3[0] WriteChannelPort4 0 => ch3[4] AHCI RCV FIS setup WriteChannelPort4 1e261400 => ch3[8] WriteChannelPort4 0 => ch3[c] WriteChannelPort4 10000006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 400040 WriteChannelPort4 400040 => ch3[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x400040 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x40c017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x0 AHCI3_0x30 (0xf773f2b0) = 0x4050000 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 imp: 0xc & 0x1 imp: 0xc & 0x2 imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 0 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 0 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7de8008, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de8008, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7de8008, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de8008, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7de8268, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de8268, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8268, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7de8268, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de8268, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8268, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b72000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f77b0230) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x47, data f773ee30, count 24, lCh 2, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773ee30) AtapiVirtToPhysAddr_: f773ee30 -> 00000000:1e276e30 set TERM ph data[0]=0:1e276e30 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7b72080, ch 2, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f77b0230 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch2[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0xa5, base 1e250080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 AtapiStartIo: next Srb f77b0200 AtapiStartIo: query PORT for next request AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xf77b0200, chan 0xb7de84c8 senseBuffer 0xb7b73000, chan 0xb7de84c8, ReqFlags 0xa AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7de84c8 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x1 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x140c017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x1404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404006 => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 1400006 WriteChannelPort4 140000e => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 1400006 CMD 0x1400006 WriteChannelPort4 1400016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 1404017 CMD 0x1404017 send CMD 0x404017, entries 0x1 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x404017 != 0x40c017) WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x4 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b72000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f77b0230) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x47, data f773ee30, count 24, lCh 2, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773ee30) AtapiVirtToPhysAddr_: f773ee30 -> 00000000:1e276e30 set TERM ph data[0]=0:1e276e30 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7b72080, ch 2, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f77b0230 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch2[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0xa5, base 1e250080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 AtapiStartIo: next Srb f77b0200 AtapiStartIo: query PORT for next request AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xf77b0200, chan 0xb7de84c8 senseBuffer 0xb7b73000, chan 0xb7de84c8, ReqFlags 0xa AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7de84c8 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x1 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x140c017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x1404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404006 => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 1400006 WriteChannelPort4 140000e => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 1400006 CMD 0x1400006 WriteChannelPort4 1400016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 1404017 CMD 0x1404017 send CMD 0x404017, entries 0x1 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x404017 != 0x40c017) WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x4 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b72000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f77b0230) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x47, data f773ee30, count 24, lCh 2, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773ee30) AtapiVirtToPhysAddr_: f773ee30 -> 00000000:1e276e30 set TERM ph data[0]=0:1e276e30 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7b72080, ch 2, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f77b0230 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch2[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0xa5, base 1e250080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 AtapiStartIo: next Srb f77b0200 AtapiStartIo: query PORT for next request AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xf77b0200, chan 0xb7de84c8 senseBuffer 0xb7b73000, chan 0xb7de84c8, ReqFlags 0xa AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7de84c8 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x1 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x140c017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x1404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 140c017 WriteChannelPort4 140c016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 final CMD 0x1404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404006 => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 1400006 WriteChannelPort4 140000e => ch2[18] ReadChannelPort4 ch2[18] = 1400006 final CMD 0x1400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 1400006 CMD 0x1400006 WriteChannelPort4 1400016 => ch2[18] ReadChannelPort4 ch2[18] = 1404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 1404016 CMD 0x1404016 WriteChannelPort4 1404017 => ch2[18] ReadChannelPort4 ch2[18] = 140c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 1404017 CMD 0x1404017 send CMD 0x404017, entries 0x1 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 Set CI WriteChannelPort4 1 => ch2[38] Send CMD START (0x404017 != 0x40c017) WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x4 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: Device 0x1 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7de84c8, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de84c8, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de84c8, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b72000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x3:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7de8728, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de8728, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b72000 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7de8728, f77b0200) AtapiStartIo: UniataRemoveRequest(b7de8728, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request ScsiPortInitialize Status 0x0 Try init 1022 7901 (hal/halx86/legacy/bussupp.c:1274) Slot assignment for 5 on bus 6 (hal/halx86/legacy/bus/pcibus.c:742) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=1, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0x6 slotNumber=0x0 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf773e000 MemIo AHCI Base: 0xf773e000 MemIo 1 Proc 0 AHCI_0x0 (0xf773e000) = 0xf737ff03 AHCI_0x4 (0xf773e004) = 0x80000000 AHCI_0x8 (0xf773e008) = 0x0 AHCI_0xc (0xf773e00c) = 0x33 AHCI_0x10 (0xf773e010) = 0x10301 check AHCI mode, GHC 0x80000000 AHCI CAP 0xf737ff03, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0x33 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0x33 Force PortMask 0x33 CommandSlots 31 Detected Channels 6 / 6 Adjusted Channels 6 AHCI version 1.31 controller with 6 ports (mask 0x33) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf773e000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 PortMask 0x3f Parameter PortMask Parameter PortMask = 0x3f Force PortMask 0x3f mask -> 6 chans Parameter NumberChannels Parameter NumberChannels = 0x6 reg -> 6 chans Final PortMask 0x3f allocate 2 Luns for 6 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x1, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773e000 MemIo 1 Proc 0 AHCI_0x0 (0xf773e000) = 0xf737ff03 AHCI_0x4 (0xf773e004) = 0x80000000 AHCI_0x8 (0xf773e008) = 0x0 AHCI_0xc (0xf773e00c) = 0x33 AHCI_0x10 (0xf773e010) = 0x10301 get GHC disable intr, GHC 0x80000000 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff03 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x33 AHCI PI mask 0x3f masked AHCI PI 0x33 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 6, 2 luns Chan 0xb7b65000 Lun 0x0 Lun ptr 0xb7b67000 Lun 0x1 Lun ptr 0xb7b67318 AtaReq 0xb7b6a000: cmd aligned b7b6a080, d=20 ahci_cmd_ptr 0xb7b6a080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b63000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b63000 AtapiVirtToPhysAddr_: b7b63000 -> 00000000:1e241000 AtapiDmaAlloc: CLP Phys BASE 1e241000 imp: 0x33 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e241000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e241400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 400040 WriteChannelPort4 400040 => ch0[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 AHCI port 0 Base: 0xf773e100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773e100) = 0x1e241000 AHCI0_0x4 (0xf773e104) = 0x0 AHCI0_0x8 (0xf773e108) = 0x1e241400 AHCI0_0xc (0xf773e10c) = 0x0 AHCI0_0x10 (0xf773e110) = 0x400040 AHCI0_0x14 (0xf773e114) = 0x0 AHCI0_0x18 (0xf773e118) = 0x40c017 AHCI0_0x1c (0xf773e11c) = 0x0 AHCI0_0x20 (0xf773e120) = 0x150 AHCI0_0x24 (0xf773e124) = 0x101 AHCI0_0x28 (0xf773e128) = 0x133 AHCI0_0x2c (0xf773e12c) = 0x0 AHCI0_0x30 (0xf773e130) = 0x4050000 AHCI0_0x34 (0xf773e134) = 0x0 AHCI0_0x38 (0xf773e138) = 0x0 AHCI0_0x3c (0xf773e13c) = 0x0 chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 6, 2 luns Chan 0xb7b65260 Lun 0x0 Lun ptr 0xb7b67630 Lun 0x1 Lun ptr 0xb7b67948 AtaReq 0xb7b6b000: cmd aligned b7b6b080, d=20 ahci_cmd_ptr 0xb7b6b080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b61000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b61000 AtapiVirtToPhysAddr_: b7b61000 -> 00000000:1e23f000 AtapiDmaAlloc: CLP Phys BASE 1e23f000 imp: 0x33 & 0x2 UniataAhciResume: lChan 1 WriteChannelPort4 0 => ch1[14] AHCI CLB setup WriteChannelPort4 1e23f000 => ch1[0] WriteChannelPort4 0 => ch1[4] AHCI RCV FIS setup WriteChannelPort4 1e23f400 => ch1[8] WriteChannelPort4 0 => ch1[c] WriteChannelPort4 10000006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 400040 WriteChannelPort4 400040 => ch1[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 AHCI port 1 Base: 0xf773e180 MemIo 1 Proc 0 AHCI1_0x0 (0xf773e180) = 0x1e23f000 AHCI1_0x4 (0xf773e184) = 0x0 AHCI1_0x8 (0xf773e188) = 0x1e23f400 AHCI1_0xc (0xf773e18c) = 0x0 AHCI1_0x10 (0xf773e190) = 0x400040 AHCI1_0x14 (0xf773e194) = 0x0 AHCI1_0x18 (0xf773e198) = 0x40c017 AHCI1_0x1c (0xf773e19c) = 0x0 AHCI1_0x20 (0xf773e1a0) = 0x150 AHCI1_0x24 (0xf773e1a4) = 0x101 AHCI1_0x28 (0xf773e1a8) = 0x133 AHCI1_0x2c (0xf773e1ac) = 0x0 AHCI1_0x30 (0xf773e1b0) = 0x4050000 AHCI1_0x34 (0xf773e1b4) = 0x0 AHCI1_0x38 (0xf773e1b8) = 0x0 AHCI1_0x3c (0xf773e1bc) = 0x0 chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 6, 2 luns Chan 0xb7b654c0 Lun 0x0 Lun ptr 0xb7b67c60 Lun 0x1 Lun ptr 0xb7b67f78 AtaReq 0xb7b6c000: cmd aligned b7b6c080, d=20 ahci_cmd_ptr 0xb7b6c080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b5f000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b5f000 AtapiVirtToPhysAddr_: b7b5f000 -> 00000000:1e23d000 AtapiDmaAlloc: CLP Phys BASE 1e23d000 imp: 0x33 & 0x4 chan 2 not implemented chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 6, 2 luns Chan 0xb7b65720 Lun 0x0 Lun ptr 0xb7b68290 Lun 0x1 Lun ptr 0xb7b685a8 AtaReq 0xb7b6d000: cmd aligned b7b6d080, d=20 ahci_cmd_ptr 0xb7b6d080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b5d000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b5d000 AtapiVirtToPhysAddr_: b7b5d000 -> 00000000:1e23b000 AtapiDmaAlloc: CLP Phys BASE 1e23b000 imp: 0x33 & 0x8 chan 3 not implemented chan 4, offs 0x300 AtapiSetupLunPtrs for channel 4 of 6, 2 luns Chan 0xb7b65980 Lun 0x0 Lun ptr 0xb7b688c0 Lun 0x1 Lun ptr 0xb7b68bd8 AtaReq 0xb7b6e000: cmd aligned b7b6e080, d=20 ahci_cmd_ptr 0xb7b6e080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b5b000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b5b000 AtapiVirtToPhysAddr_: b7b5b000 -> 00000000:1e239000 AtapiDmaAlloc: CLP Phys BASE 1e239000 imp: 0x33 & 0x10 UniataAhciResume: lChan 4 WriteChannelPort4 0 => ch4[14] AHCI CLB setup WriteChannelPort4 1e239000 => ch4[0] WriteChannelPort4 0 => ch4[4] AHCI RCV FIS setup WriteChannelPort4 1e239400 => ch4[8] WriteChannelPort4 0 => ch4[c] WriteChannelPort4 10000006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 400040 WriteChannelPort4 400040 => ch4[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 AHCI port 4 Base: 0xf773e300 MemIo 1 Proc 0 AHCI4_0x0 (0xf773e300) = 0x1e239000 AHCI4_0x4 (0xf773e304) = 0x0 AHCI4_0x8 (0xf773e308) = 0x1e239400 AHCI4_0xc (0xf773e30c) = 0x0 AHCI4_0x10 (0xf773e310) = 0x400040 AHCI4_0x14 (0xf773e314) = 0x0 AHCI4_0x18 (0xf773e318) = 0x40c017 AHCI4_0x1c (0xf773e31c) = 0x0 AHCI4_0x20 (0xf773e320) = 0x150 AHCI4_0x24 (0xf773e324) = 0x101 AHCI4_0x28 (0xf773e328) = 0x133 AHCI4_0x2c (0xf773e32c) = 0x0 AHCI4_0x30 (0xf773e330) = 0x4050000 AHCI4_0x34 (0xf773e334) = 0x0 AHCI4_0x38 (0xf773e338) = 0x0 AHCI4_0x3c (0xf773e33c) = 0x0 chan 5, offs 0x380 AtapiSetupLunPtrs for channel 5 of 6, 2 luns Chan 0xb7b65be0 Lun 0x0 Lun ptr 0xb7b68ef0 Lun 0x1 Lun ptr 0xb7b69208 AtaReq 0xb7b6f000: cmd aligned b7b6f080, d=20 ahci_cmd_ptr 0xb7b6f080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b59000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b59000 AtapiVirtToPhysAddr_: b7b59000 -> 00000000:1e237000 AtapiDmaAlloc: CLP Phys BASE 1e237000 imp: 0x33 & 0x20 UniataAhciResume: lChan 5 WriteChannelPort4 0 => ch5[14] AHCI CLB setup WriteChannelPort4 1e237000 => ch5[0] WriteChannelPort4 0 => ch5[4] AHCI RCV FIS setup WriteChannelPort4 1e237400 => ch5[8] WriteChannelPort4 0 => ch5[c] WriteChannelPort4 10000006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 400040 WriteChannelPort4 400040 => ch5[10] SError 0x40d0000, IS 0x400040 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 AHCI port 5 Base: 0xf773e380 MemIo 1 Proc 0 AHCI5_0x0 (0xf773e380) = 0x1e237000 AHCI5_0x4 (0xf773e384) = 0x0 AHCI5_0x8 (0xf773e388) = 0x1e237400 AHCI5_0xc (0xf773e38c) = 0x0 AHCI5_0x10 (0xf773e390) = 0x400040 AHCI5_0x14 (0xf773e394) = 0x0 AHCI5_0x18 (0xf773e398) = 0x40c017 AHCI5_0x1c (0xf773e39c) = 0x0 AHCI5_0x20 (0xf773e3a0) = 0x150 AHCI5_0x24 (0xf773e3a4) = 0x101 AHCI5_0x28 (0xf773e3a8) = 0x123 AHCI5_0x2c (0xf773e3ac) = 0x0 AHCI5_0x30 (0xf773e3b0) = 0x40d0000 AHCI5_0x34 (0xf773e3b4) = 0x0 AHCI5_0x38 (0xf773e3b8) = 0x0 AHCI5_0x3c (0xf773e3bc) = 0x0 simplexOnly = 0 (2)!MasterDev update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 10, Level2 0, Vector 10, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x6, channel 0x0 de 0xb7de72b4, Channel 0x0 chan = 0xb7b65000 AtapiSetupLunPtrs for channel 0 of 6, 2 luns Chan 0xb7b65000 Lun 0x0 Lun ptr 0xb7b67000 Lun 0x1 Lun ptr 0xb7b67318 AtaReq 0xb7b6a000: cmd aligned b7b6a080, d=20 ahci_cmd_ptr 0xb7b6a080 AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773e120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773e128), Mem: AtapiDmaAlloc: AHCI already initialized b7b63000 de 0xb7de72b4, Channel 0x1 chan = 0xb7b65260 AtapiSetupLunPtrs for channel 1 of 6, 2 luns Chan 0xb7b65260 Lun 0x0 Lun ptr 0xb7b67630 Lun 0x1 Lun ptr 0xb7b67948 AtaReq 0xb7b6b000: cmd aligned b7b6b080, d=20 ahci_cmd_ptr 0xb7b6b080 AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan 1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773e1a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773e1a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b61000 de 0xb7de72b4, Channel 0x2 chan = 0xb7b654c0 AtapiSetupLunPtrs for channel 2 of 6, 2 luns Chan 0xb7b654c0 Lun 0x0 Lun ptr 0xb7b67c60 Lun 0x1 Lun ptr 0xb7b67f78 AtaReq 0xb7b6c000: cmd aligned b7b6c080, d=20 ahci_cmd_ptr 0xb7b6c080 AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan 2 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773e220), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773e228), Mem: AtapiDmaAlloc: AHCI already initialized b7b5f000 de 0xb7de72b4, Channel 0x3 chan = 0xb7b65720 AtapiSetupLunPtrs for channel 3 of 6, 2 luns Chan 0xb7b65720 Lun 0x0 Lun ptr 0xb7b68290 Lun 0x1 Lun ptr 0xb7b685a8 AtaReq 0xb7b6d000: cmd aligned b7b6d080, d=20 ahci_cmd_ptr 0xb7b6d080 AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan 3 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773e2a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773e2a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b5d000 de 0xb7de72b4, Channel 0x4 chan = 0xb7b65980 AtapiSetupLunPtrs for channel 4 of 6, 2 luns Chan 0xb7b65980 Lun 0x0 Lun ptr 0xb7b688c0 Lun 0x1 Lun ptr 0xb7b68bd8 AtaReq 0xb7b6e000: cmd aligned b7b6e080, d=20 ahci_cmd_ptr 0xb7b6e080 AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan 4 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773e320), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773e328), Mem: AtapiDmaAlloc: AHCI already initialized b7b5b000 de 0xb7de72b4, Channel 0x5 chan = 0xb7b65be0 AtapiSetupLunPtrs for channel 5 of 6, 2 luns Chan 0xb7b65be0 Lun 0x0 Lun ptr 0xb7b68ef0 Lun 0x1 Lun ptr 0xb7b69208 AtaReq 0xb7b6f000: cmd aligned b7b6f080, d=20 ahci_cmd_ptr 0xb7b6f080 AtapiReadChipConfig: devExt 0xb7de72b4 AtapiReadChipConfig: dev 0x1, ph chan 5 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773e3a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773e3a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b59000 exit: init spinlock MasterDev=0x0, NumberChannels=0x6, Isr2DevObj=0x0 Init ISR: Multichannel native mode, go... Create DO DO name: len(38, 38), \Device\uniata1_2ch HalGetInterruptVector OrigAdapterInterfaceType=5 SystemIoBusNumber=7 BusInterruptLevel=10 BusInterruptVector=10 isr2_de 0xb7de7e40 isr2_vector 0x3a isr2_irql 0x11 isr2_affinity 0x1 IoConnectInterrupt MasterDev=0x0, NumberChannels=0x6, Isr2DevObj=0xb7de7d88 final chan[6] InterruptMode: 0, Level 10, Level2 0, Vector 10, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773e000 MemIo 1 Proc 0 AHCI_0x0 (0xf773e000) = 0xf737ff03 AHCI_0x4 (0xf773e004) = 0x80000002 AHCI_0x8 (0xf773e008) = 0x0 AHCI_0xc (0xf773e00c) = 0x33 AHCI_0x10 (0xf773e010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff03 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x33 AHCI PI mask 0x3f masked AHCI PI 0x33 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 6, 2 luns Chan 0xb7b65000 Lun 0x0 Lun ptr 0xb7b67000 Lun 0x1 Lun ptr 0xb7b67318 AtaReq 0xb7b6a000: cmd aligned b7b6a080, d=20 ahci_cmd_ptr 0xb7b6a080 AtapiDmaAlloc: AHCI already initialized b7b63000 imp: 0x33 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e241000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e241400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 400040 WriteChannelPort4 400040 => ch0[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 AHCI port 0 Base: 0xf773e100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773e100) = 0x1e241000 AHCI0_0x4 (0xf773e104) = 0x0 AHCI0_0x8 (0xf773e108) = 0x1e241400 AHCI0_0xc (0xf773e10c) = 0x0 AHCI0_0x10 (0xf773e110) = 0x400040 AHCI0_0x14 (0xf773e114) = 0x0 AHCI0_0x18 (0xf773e118) = 0x40c017 AHCI0_0x1c (0xf773e11c) = 0x0 AHCI0_0x20 (0xf773e120) = 0x150 AHCI0_0x24 (0xf773e124) = 0x101 AHCI0_0x28 (0xf773e128) = 0x133 AHCI0_0x2c (0xf773e12c) = 0x0 AHCI0_0x30 (0xf773e130) = 0x4050000 AHCI0_0x34 (0xf773e134) = 0x0 AHCI0_0x38 (0xf773e138) = 0x0 AHCI0_0x3c (0xf773e13c) = 0x0 chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 6, 2 luns Chan 0xb7b65260 Lun 0x0 Lun ptr 0xb7b67630 Lun 0x1 Lun ptr 0xb7b67948 AtaReq 0xb7b6b000: cmd aligned b7b6b080, d=20 ahci_cmd_ptr 0xb7b6b080 AtapiDmaAlloc: AHCI already initialized b7b61000 imp: 0x33 & 0x2 UniataAhciResume: lChan 1 WriteChannelPort4 0 => ch1[14] AHCI CLB setup WriteChannelPort4 1e23f000 => ch1[0] WriteChannelPort4 0 => ch1[4] AHCI RCV FIS setup WriteChannelPort4 1e23f400 => ch1[8] WriteChannelPort4 0 => ch1[c] WriteChannelPort4 10000006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 400040 WriteChannelPort4 400040 => ch1[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 AHCI port 1 Base: 0xf773e180 MemIo 1 Proc 0 AHCI1_0x0 (0xf773e180) = 0x1e23f000 AHCI1_0x4 (0xf773e184) = 0x0 AHCI1_0x8 (0xf773e188) = 0x1e23f400 AHCI1_0xc (0xf773e18c) = 0x0 AHCI1_0x10 (0xf773e190) = 0x400040 AHCI1_0x14 (0xf773e194) = 0x0 AHCI1_0x18 (0xf773e198) = 0x40c017 AHCI1_0x1c (0xf773e19c) = 0x0 AHCI1_0x20 (0xf773e1a0) = 0x150 AHCI1_0x24 (0xf773e1a4) = 0x101 AHCI1_0x28 (0xf773e1a8) = 0x133 AHCI1_0x2c (0xf773e1ac) = 0x0 AHCI1_0x30 (0xf773e1b0) = 0x4050000 AHCI1_0x34 (0xf773e1b4) = 0x0 AHCI1_0x38 (0xf773e1b8) = 0x0 AHCI1_0x3c (0xf773e1bc) = 0x0 chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 6, 2 luns Chan 0xb7b654c0 Lun 0x0 Lun ptr 0xb7b67c60 Lun 0x1 Lun ptr 0xb7b67f78 AtaReq 0xb7b6c000: cmd aligned b7b6c080, d=20 ahci_cmd_ptr 0xb7b6c080 AtapiDmaAlloc: AHCI already initialized b7b5f000 imp: 0x33 & 0x4 chan 2 not implemented chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 6, 2 luns Chan 0xb7b65720 Lun 0x0 Lun ptr 0xb7b68290 Lun 0x1 Lun ptr 0xb7b685a8 AtaReq 0xb7b6d000: cmd aligned b7b6d080, d=20 ahci_cmd_ptr 0xb7b6d080 AtapiDmaAlloc: AHCI already initialized b7b5d000 imp: 0x33 & 0x8 chan 3 not implemented chan 4, offs 0x300 AtapiSetupLunPtrs for channel 4 of 6, 2 luns Chan 0xb7b65980 Lun 0x0 Lun ptr 0xb7b688c0 Lun 0x1 Lun ptr 0xb7b68bd8 AtaReq 0xb7b6e000: cmd aligned b7b6e080, d=20 ahci_cmd_ptr 0xb7b6e080 AtapiDmaAlloc: AHCI already initialized b7b5b000 imp: 0x33 & 0x10 UniataAhciResume: lChan 4 WriteChannelPort4 0 => ch4[14] AHCI CLB setup WriteChannelPort4 1e239000 => ch4[0] WriteChannelPort4 0 => ch4[4] AHCI RCV FIS setup WriteChannelPort4 1e239400 => ch4[8] WriteChannelPort4 0 => ch4[c] WriteChannelPort4 10000006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 400040 WriteChannelPort4 400040 => ch4[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 AHCI port 4 Base: 0xf773e300 MemIo 1 Proc 0 AHCI4_0x0 (0xf773e300) = 0x1e239000 AHCI4_0x4 (0xf773e304) = 0x0 AHCI4_0x8 (0xf773e308) = 0x1e239400 AHCI4_0xc (0xf773e30c) = 0x0 AHCI4_0x10 (0xf773e310) = 0x400040 AHCI4_0x14 (0xf773e314) = 0x0 AHCI4_0x18 (0xf773e318) = 0x40c017 AHCI4_0x1c (0xf773e31c) = 0x0 AHCI4_0x20 (0xf773e320) = 0x150 AHCI4_0x24 (0xf773e324) = 0x101 AHCI4_0x28 (0xf773e328) = 0x133 AHCI4_0x2c (0xf773e32c) = 0x0 AHCI4_0x30 (0xf773e330) = 0x4050000 AHCI4_0x34 (0xf773e334) = 0x0 AHCI4_0x38 (0xf773e338) = 0x0 AHCI4_0x3c (0xf773e33c) = 0x0 chan 5, offs 0x380 AtapiSetupLunPtrs for channel 5 of 6, 2 luns Chan 0xb7b65be0 Lun 0x0 Lun ptr 0xb7b68ef0 Lun 0x1 Lun ptr 0xb7b69208 AtaReq 0xb7b6f000: cmd aligned b7b6f080, d=20 ahci_cmd_ptr 0xb7b6f080 AtapiDmaAlloc: AHCI already initialized b7b59000 imp: 0x33 & 0x20 UniataAhciResume: lChan 5 WriteChannelPort4 0 => ch5[14] AHCI CLB setup WriteChannelPort4 1e237000 => ch5[0] WriteChannelPort4 0 => ch5[4] AHCI RCV FIS setup WriteChannelPort4 1e237400 => ch5[8] WriteChannelPort4 0 => ch5[c] WriteChannelPort4 10000006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 400040 WriteChannelPort4 400040 => ch5[10] SError 0x40d0000, IS 0x400040 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 AHCI port 5 Base: 0xf773e380 MemIo 1 Proc 0 AHCI5_0x0 (0xf773e380) = 0x1e237000 AHCI5_0x4 (0xf773e384) = 0x0 AHCI5_0x8 (0xf773e388) = 0x1e237400 AHCI5_0xc (0xf773e38c) = 0x0 AHCI5_0x10 (0xf773e390) = 0x400040 AHCI5_0x14 (0xf773e394) = 0x0 AHCI5_0x18 (0xf773e398) = 0x40c017 AHCI5_0x1c (0xf773e39c) = 0x0 AHCI5_0x20 (0xf773e3a0) = 0x150 AHCI5_0x24 (0xf773e3a4) = 0x101 AHCI5_0x28 (0xf773e3a8) = 0x123 AHCI5_0x2c (0xf773e3ac) = 0x0 AHCI5_0x30 (0xf773e3b0) = 0x40d0000 AHCI5_0x34 (0xf773e3b4) = 0x0 AHCI5_0x38 (0xf773e3b8) = 0x0 AHCI5_0x3c (0xf773e3bc) = 0x0 imp: 0x33 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 40c017 WriteChannelPort4 40c016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 TFD 0x150 AHCI port 0 Base: 0xf773e100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773e100) = 0x1e241000 AHCI0_0x4 (0xf773e104) = 0x0 AHCI0_0x8 (0xf773e108) = 0x1e241400 AHCI0_0xc (0xf773e10c) = 0x0 AHCI0_0x10 (0xf773e110) = 0x0 AHCI0_0x14 (0xf773e114) = 0x0 AHCI0_0x18 (0xf773e118) = 0x404016 AHCI0_0x1c (0xf773e11c) = 0x0 AHCI0_0x20 (0xf773e120) = 0x150 AHCI0_0x24 (0xf773e124) = 0x101 AHCI0_0x28 (0xf773e128) = 0x133 AHCI0_0x2c (0xf773e12c) = 0x300 AHCI0_0x30 (0xf773e130) = 0x0 AHCI0_0x34 (0xf773e134) = 0x0 AHCI0_0x38 (0xf773e138) = 0x0 AHCI0_0x3c (0xf773e13c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 WriteChannelPort4 f900003f => ch0[14] check PM UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 40c017 WriteChannelPort4 40c016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 400006 WriteChannelPort4 40000e => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 404017 WriteChannelPort4 404016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 400006 WriteChannelPort4 40000e => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7de72f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de7e80, AtaReq 0xb7b6a000, CMD 0xb7b6a080 ph 0 AHCI setup FIS b7b6a080, ch 0, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b7de72f8, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b7b6a080) AtapiVirtToPhysAddr_: b7b6a080 -> 00000000:1e248080 get Phys(data[0]=b7de72f8) AtapiVirtToPhysAddr_: b7de72f8 -> 00000000:1e4c52f8 set TERM ph data[0]=0:1e4c52f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b6a000 AHCI AtaReq CMD 0xb7b6a080 (ph 0x1e248080) prd_length 0x1, flags 0x5, base 1e248080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 2 IS 0x2 WriteChannelPort4 2 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: DATA AUS08 0 FW: 0Q29 S/N: I22402003349 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 14c, CAPs 0x850e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 0/0 PhysLogSectorSize 0x4000, 0x100, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 1 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x7f0 UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1e4815 NativeNumOfSectors 0x773bd2b0 Update NumOfSectors to 0x773bd2b0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de7e80, AtaReq 0xb7b6a000, CMD 0xb7b6a080 ph 1e248080 AHCI setup FIS b7b6a080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b6a000 AHCI AtaReq CMD 0xb7b6a080 (ph 0x1e248080) prd_length 0x0, flags 0x5, base 1e248080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x773bd2af 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1e4815 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=f240/80/fc Geometry: C 0xf240 (0xf240) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b67000 S/N:ADATA_SU800_____________________________-2I4220003394________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de7e80, AtaReq 0xb7b6a000, CMD 0xb7b6a080 ph 1e248080 AHCI setup FIS b7b6a080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b6a000 AHCI AtaReq CMD 0xb7b6a080 (ph 0x1e248080) prd_length 0x0, flags 0x5, base 1e248080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de7e80, AtaReq 0xb7b6a000, CMD 0xb7b6a080 ph 1e248080 AHCI setup FIS b7b6a080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b6a000 AHCI AtaReq CMD 0xb7b6a080 (ph 0x1e248080) prd_length 0x0, flags 0x5, base 1e248080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de7e80, AtaReq 0xb7b6a000, CMD 0xb7b6a080 ph 1e248080 AHCI setup FIS b7b6a080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b6a000 AHCI AtaReq CMD 0xb7b6a080 (ph 0x1e248080) prd_length 0x0, flags 0x5, base 1e248080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de7e80, AtaReq 0xb7b6a000, CMD 0xb7b6a080 ph 1e248080 AHCI setup FIS b7b6a080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b6a000 AHCI AtaReq CMD 0xb7b6a080 (ph 0x1e248080) prd_length 0x0, flags 0x5, base 1e248080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x33 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x49 mode imp: 0x33 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiHwInitialize: lChannel 0x0, dev 1 imp: 0x33 & 0x2 AtapiChipInit: dev 0xffffffff, ph chan 1, c 1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 1 WriteChannelPort4 0 => ch1[14] UniataAhciHardReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 40c017 WriteChannelPort4 40c016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 TFD 0x150 AHCI port 1 Base: 0xf773e180 MemIo 1 Proc 0 AHCI1_0x0 (0xf773e180) = 0x1e23f000 AHCI1_0x4 (0xf773e184) = 0x0 AHCI1_0x8 (0xf773e188) = 0x1e23f400 AHCI1_0xc (0xf773e18c) = 0x0 AHCI1_0x10 (0xf773e190) = 0x0 AHCI1_0x14 (0xf773e194) = 0x0 AHCI1_0x18 (0xf773e198) = 0x404016 AHCI1_0x1c (0xf773e19c) = 0x0 AHCI1_0x20 (0xf773e1a0) = 0x150 AHCI1_0x24 (0xf773e1a4) = 0x101 AHCI1_0x28 (0xf773e1a8) = 0x133 AHCI1_0x2c (0xf773e1ac) = 0x300 AHCI1_0x30 (0xf773e1b0) = 0x0 AHCI1_0x34 (0xf773e1b4) = 0x0 AHCI1_0x38 (0xf773e1b8) = 0x0 AHCI1_0x3c (0xf773e1bc) = 0x0 ReadChannelPort4 ch1[24] = 101 sig: 0x101 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 WriteChannelPort4 f900003f => ch1[14] check PM UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 40c017 WriteChannelPort4 40c016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 400006 WriteChannelPort4 40000e => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_1: 0 WriteChannelPort4 0 => ch1[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 404017 WriteChannelPort4 404016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 400006 WriteChannelPort4 40000e => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7de72f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7ec0, AtaReq 0xb7b6b000, CMD 0xb7b6b080 ph 0 AHCI setup FIS b7b6b080, ch 1, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b7de72f8, count 200, lCh 1, dev 0 get Phys(AHCI_CMD=b7b6b080) AtapiVirtToPhysAddr_: b7b6b080 -> 00000000:1e249080 get Phys(data[0]=b7de72f8) AtapiVirtToPhysAddr_: b7de72f8 -> 00000000:1e4c52f8 set TERM ph data[0]=0:1e4c52f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b6b000 AHCI AtaReq CMD 0xb7b6b080 (ph 0x1e249080) prd_length 0x1, flags 0x5, base 1e249080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 2 IS 0x2 WriteChannelPort4 2 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 IssueIdentify: Status after read words 0x50 Model: aSsmnu gSS D58 0VE O FW: ME0T S/N: 2SBRXNHB134025 Z Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 60 SATA support: 16c, CAPs 0x850e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 0/0 PhysLogSectorSize 0x4000, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 1 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x3fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0xec93d NativeNumOfSectors 0x3a386030 Update NumOfSectors to 0x3a386030 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7ec0, AtaReq 0xb7b6b000, CMD 0xb7b6b080 ph 1e249080 AHCI setup FIS b7b6b080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b6b000 AHCI AtaReq CMD 0xb7b6b080 (ph 0x1e249080) prd_length 0x0, flags 0x5, base 1e249080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 NativeNumOfSectors 0x3a38602f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0xec93d Use GEOM_STD, CHS=ed81/ff/3f Geometry: C 0xed81 (0xed81) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b67630 S/N:Samsung_SSD_850_EVO_500GB_______________-S2RBNXBH310452Z_____ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x2 AtapiEnableInterrupts_1: 1 WriteChannelPort4 fd4000ff => ch1[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x1, dev 0 AtapiDisableInterrupts_1: 0 WriteChannelPort4 0 => ch1[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7ec0, AtaReq 0xb7b6b000, CMD 0xb7b6b080 ph 1e249080 AHCI setup FIS b7b6b080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b6b000 AHCI AtaReq CMD 0xb7b6b080 (ph 0x1e249080) prd_length 0x0, flags 0x5, base 1e249080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7ec0, AtaReq 0xb7b6b000, CMD 0xb7b6b080 ph 1e249080 AHCI setup FIS b7b6b080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b6b000 AHCI AtaReq CMD 0xb7b6b080 (ph 0x1e249080) prd_length 0x0, flags 0x5, base 1e249080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7ec0, AtaReq 0xb7b6b000, CMD 0xb7b6b080 ph 1e249080 AHCI setup FIS b7b6b080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b6b000 AHCI AtaReq CMD 0xb7b6b080 (ph 0x1e249080) prd_length 0x0, flags 0x5, base 1e249080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 1/0 AtapiDisableInterrupts_1: 1 WriteChannelPort4 0 => ch1[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7ec0, AtaReq 0xb7b6b000, CMD 0xb7b6b080 ph 1e249080 AHCI setup FIS b7b6b080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b6b000 AHCI AtaReq CMD 0xb7b6b080 (ph 0x1e249080) prd_length 0x0, flags 0x5, base 1e249080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 imp: 0x33 & 0x2 AtapiEnableInterrupts_1: 2 WriteChannelPort4 0 => ch1[14] Using 0x49 mode imp: 0x33 & 0x2 AtapiEnableInterrupts_1: 1 WriteChannelPort4 fd4000ff => ch1[14] AtapiHwInitialize: lChannel 0x1, dev 1 imp: 0x33 & 0x4 imp: 0x33 & 0x8 imp: 0x33 & 0x10 AtapiChipInit: dev 0xffffffff, ph chan 4, c 4 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 4 WriteChannelPort4 0 => ch4[14] UniataAhciHardReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 40c017 WriteChannelPort4 40c016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 TFD 0x150 AHCI port 4 Base: 0xf773e300 MemIo 1 Proc 0 AHCI4_0x0 (0xf773e300) = 0x1e239000 AHCI4_0x4 (0xf773e304) = 0x0 AHCI4_0x8 (0xf773e308) = 0x1e239400 AHCI4_0xc (0xf773e30c) = 0x0 AHCI4_0x10 (0xf773e310) = 0x0 AHCI4_0x14 (0xf773e314) = 0x0 AHCI4_0x18 (0xf773e318) = 0x404016 AHCI4_0x1c (0xf773e31c) = 0x0 AHCI4_0x20 (0xf773e320) = 0x150 AHCI4_0x24 (0xf773e324) = 0x101 AHCI4_0x28 (0xf773e328) = 0x133 AHCI4_0x2c (0xf773e32c) = 0x300 AHCI4_0x30 (0xf773e330) = 0x0 AHCI4_0x34 (0xf773e334) = 0x0 AHCI4_0x38 (0xf773e338) = 0x0 AHCI4_0x3c (0xf773e33c) = 0x0 ReadChannelPort4 ch4[24] = 101 sig: 0x101 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 WriteChannelPort4 f900003f => ch4[14] check PM UniataAhciSoftReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 40c017 WriteChannelPort4 40c016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 4 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 4 send CLO ReadChannelPort4 ch4[18] = 400006 WriteChannelPort4 40000e => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_4: 0 WriteChannelPort4 0 => ch4[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 404017 WriteChannelPort4 404016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 4 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 4 send CLO ReadChannelPort4 ch4[18] = 400006 WriteChannelPort4 40000e => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7de72f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 0 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b7de72f8, count 200, lCh 4, dev 0 get Phys(AHCI_CMD=b7b6e080) AtapiVirtToPhysAddr_: b7b6e080 -> 00000000:1e24c080 get Phys(data[0]=b7de72f8) AtapiVirtToPhysAddr_: b7de72f8 -> 00000000:1e4c52f8 set TERM ph data[0]=0:1e4c52f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x1, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 2 IS 0x2 WriteChannelPort4 2 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 IssueIdentify: Status after read words 0x50 Model: DW CDW012SX12-R4B10T FW: 300. S/N: W -DXW17CA439182 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 240 SATA support: 24c, CAPs 0xff0e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x6003, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 5400 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x3fe UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1d9265 NativeNumOfSectors 0x74706db0 Update NumOfSectors to 0x74706db0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 NativeNumOfSectors 0x74706daf 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1d9265 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=ec93/80/fc Geometry: C 0xec93 (0xec93) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b688c0 S/N:WDC_WD10S21X-24R1BT0-SSHD-8GB___________-_____WD-WX71AC341928 IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x10 AtapiEnableInterrupts_4: 1 WriteChannelPort4 fd4000ff => ch4[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x4, dev 0 AtapiDisableInterrupts_4: 0 WriteChannelPort4 0 => ch4[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 1 CI 0x1 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 4/0 AtapiDisableInterrupts_4: 1 WriteChannelPort4 0 => ch4[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de7f80, AtaReq 0xb7b6e000, CMD 0xb7b6e080 ph 1e24c080 AHCI setup FIS b7b6e080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b6e000 AHCI AtaReq CMD 0xb7b6e080 (ph 0x1e24c080) prd_length 0x0, flags 0x5, base 1e24c080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 1 CI 0x1 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 imp: 0x33 & 0x10 AtapiEnableInterrupts_4: 2 WriteChannelPort4 0 => ch4[14] Using 0x49 mode imp: 0x33 & 0x10 AtapiEnableInterrupts_4: 1 WriteChannelPort4 fd4000ff => ch4[14] AtapiHwInitialize: lChannel 0x4, dev 1 imp: 0x33 & 0x20 AtapiChipInit: dev 0xffffffff, ph chan 5, c 5 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 5 WriteChannelPort4 0 => ch5[14] UniataAhciHardReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 40c017 WriteChannelPort4 40c016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 TFD 0x150 AHCI port 5 Base: 0xf773e380 MemIo 1 Proc 0 AHCI5_0x0 (0xf773e380) = 0x1e237000 AHCI5_0x4 (0xf773e384) = 0x0 AHCI5_0x8 (0xf773e388) = 0x1e237400 AHCI5_0xc (0xf773e38c) = 0x0 AHCI5_0x10 (0xf773e390) = 0x0 AHCI5_0x14 (0xf773e394) = 0x0 AHCI5_0x18 (0xf773e398) = 0x404016 AHCI5_0x1c (0xf773e39c) = 0x0 AHCI5_0x20 (0xf773e3a0) = 0x150 AHCI5_0x24 (0xf773e3a4) = 0x101 AHCI5_0x28 (0xf773e3a8) = 0x123 AHCI5_0x2c (0xf773e3ac) = 0x300 AHCI5_0x30 (0xf773e3b0) = 0x0 AHCI5_0x34 (0xf773e3b4) = 0x0 AHCI5_0x38 (0xf773e3b8) = 0x0 AHCI5_0x3c (0xf773e3bc) = 0x0 ReadChannelPort4 ch5[24] = 101 sig: 0x101 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 WriteChannelPort4 f900003f => ch5[14] check PM UniataAhciSoftReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 40c017 WriteChannelPort4 40c016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 5 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 5 send CLO ReadChannelPort4 ch5[18] = 400006 WriteChannelPort4 40000e => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_5: 0 WriteChannelPort4 0 => ch5[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 404017 WriteChannelPort4 404016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 5 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 5 send CLO ReadChannelPort4 ch5[18] = 400006 WriteChannelPort4 40000e => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7de72f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 0 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7de72f8, count 200, lCh 5, dev 0 get Phys(AHCI_CMD=b7b6f080) AtapiVirtToPhysAddr_: b7b6f080 -> 00000000:1e24d080 get Phys(data[0]=b7de72f8) AtapiVirtToPhysAddr_: b7de72f8 -> 00000000:1e4c52f8 set TERM ph data[0]=0:1e4c52f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x1, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 2 IS 0x2 WriteChannelPort4 2 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 IssueIdentify: Status after read words 0x50 Model: OTHSBI AQM10BA1D00 FW: XA00 S/N: 2 43F6S6SA Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/3f SATA: 40 SATA support: 4c, CAPs 0xf06 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x6003, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 5400 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1f8 UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1d9265 NativeNumOfSectors 0x74706db0 Update NumOfSectors to 0x74706db0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 1e24d080 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x0, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 NativeNumOfSectors 0x74706daf 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1d9265 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=ec93/80/fc Geometry: C 0xec93 (0xec93) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) InitBadBlocks local LunExt 0xb7b68ef0 S/N:TOSHIBA_MQ01ABD100______________________-___________2346F6SAS IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x20 AtapiEnableInterrupts_5: 1 WriteChannelPort4 fd4000ff => ch5[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x5, dev 0 AtapiDisableInterrupts_5: 0 WriteChannelPort4 0 => ch5[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 1e24d080 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x0, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 1 CI 0x1 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 1e24d080 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x0, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 1e24d080 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x0, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 1e24d080 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x0, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x5 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 5/0 AtapiDisableInterrupts_5: 1 WriteChannelPort4 0 => ch5[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x45 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7fc0, AtaReq 0xb7b6f000, CMD 0xb7b6f080 ph 1e24d080 AHCI setup FIS b7b6f080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b6f000 AHCI AtaReq CMD 0xb7b6f080 (ph 0x1e24d080) prd_length 0x0, flags 0x5, base 1e24d080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 imp: 0x33 & 0x20 AtapiEnableInterrupts_5: 2 WriteChannelPort4 0 => ch5[14] Using 0x48 mode imp: 0x33 & 0x20 AtapiEnableInterrupts_5: 1 WriteChannelPort4 fd4000ff => ch5[14] AtapiHwInitialize: lChannel 0x5, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x1 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b48000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b48000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b65000, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65000, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65000, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 404017 WriteChannelPort4 404016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 400006 WriteChannelPort4 40000e => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b65000, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65000, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65000, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x2 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b48000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b48000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x1:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b65260, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65260, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65260, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 404017 WriteChannelPort4 404016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 400006 WriteChannelPort4 40000e => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b65260, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65260, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65260, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b654c0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b654c0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b654c0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b654c0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b654c0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b654c0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x8 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b65720, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65720, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65720, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x8 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b65720, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65720, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65720, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x10 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b48000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b48000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x4:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b65980, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65980, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65980, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x10 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 404017 WriteChannelPort4 404016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 4 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 4 send CLO ReadChannelPort4 ch4[18] = 400006 WriteChannelPort4 40000e => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b65980, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65980, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65980, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x5:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x20 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b48000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b48000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x5:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b65be0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65be0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65be0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x5:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x5:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x20 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b48000 SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 404017 WriteChannelPort4 404016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 5 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 5 send CLO ReadChannelPort4 ch5[18] = 400006 WriteChannelPort4 40000e => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b65be0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b65be0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b65be0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x6:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x6:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x6:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request (hal/halx86/legacy/bussupp.c:1274) Slot assignment for 5 on bus 10 (hal/halx86/legacy/bus/pcibus.c:742) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=1, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0xa slotNumber=0x0 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf773d000 MemIo AHCI Base: 0xf773d000 MemIo 1 Proc 0 AHCI_0x0 (0xf773d000) = 0xf737ff03 AHCI_0x4 (0xf773d004) = 0x80000002 AHCI_0x8 (0xf773d008) = 0x0 AHCI_0xc (0xf773d00c) = 0x33 AHCI_0x10 (0xf773d010) = 0x10301 check AHCI mode, GHC 0x80000002 AHCI CAP 0xf737ff03, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0x33 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0x33 Force PortMask 0x33 CommandSlots 31 Detected Channels 6 / 6 Adjusted Channels 6 AHCI version 1.31 controller with 6 ports (mask 0x33) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf773d000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 PortMask 0x3f Parameter PortMask Parameter PortMask = 0x3f Force PortMask 0x3f mask -> 6 chans Parameter NumberChannels Parameter NumberChannels = 0x6 reg -> 6 chans Final PortMask 0x3f allocate 2 Luns for 6 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x1, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773d000 MemIo 1 Proc 0 AHCI_0x0 (0xf773d000) = 0xf737ff03 AHCI_0x4 (0xf773d004) = 0x80000002 AHCI_0x8 (0xf773d008) = 0x0 AHCI_0xc (0xf773d00c) = 0x33 AHCI_0x10 (0xf773d010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff03 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x33 AHCI PI mask 0x3f masked AHCI PI 0x33 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 6, 2 luns Chan 0xb7b39000 Lun 0x0 Lun ptr 0xb7b3b000 Lun 0x1 Lun ptr 0xb7b3b318 AtaReq 0xb7b3e000: cmd aligned b7b3e080, d=20 ahci_cmd_ptr 0xb7b3e080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b37000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b37000 AtapiVirtToPhysAddr_: b7b37000 -> 00000000:1e215000 AtapiDmaAlloc: CLP Phys BASE 1e215000 imp: 0x33 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e215000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e215400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 400040 WriteChannelPort4 400040 => ch0[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 AHCI port 0 Base: 0xf773d100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773d100) = 0x1e215000 AHCI0_0x4 (0xf773d104) = 0x0 AHCI0_0x8 (0xf773d108) = 0x1e215400 AHCI0_0xc (0xf773d10c) = 0x0 AHCI0_0x10 (0xf773d110) = 0x400040 AHCI0_0x14 (0xf773d114) = 0x0 AHCI0_0x18 (0xf773d118) = 0x40c017 AHCI0_0x1c (0xf773d11c) = 0x0 AHCI0_0x20 (0xf773d120) = 0x150 AHCI0_0x24 (0xf773d124) = 0x101 AHCI0_0x28 (0xf773d128) = 0x133 AHCI0_0x2c (0xf773d12c) = 0x0 AHCI0_0x30 (0xf773d130) = 0x4050000 AHCI0_0x34 (0xf773d134) = 0x0 AHCI0_0x38 (0xf773d138) = 0x0 AHCI0_0x3c (0xf773d13c) = 0x0 chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 6, 2 luns Chan 0xb7b39260 Lun 0x0 Lun ptr 0xb7b3b630 Lun 0x1 Lun ptr 0xb7b3b948 AtaReq 0xb7b3f000: cmd aligned b7b3f080, d=20 ahci_cmd_ptr 0xb7b3f080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b35000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b35000 AtapiVirtToPhysAddr_: b7b35000 -> 00000000:1e213000 AtapiDmaAlloc: CLP Phys BASE 1e213000 imp: 0x33 & 0x2 UniataAhciResume: lChan 1 WriteChannelPort4 0 => ch1[14] AHCI CLB setup WriteChannelPort4 1e213000 => ch1[0] WriteChannelPort4 0 => ch1[4] AHCI RCV FIS setup WriteChannelPort4 1e213400 => ch1[8] WriteChannelPort4 0 => ch1[c] WriteChannelPort4 10000006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 400040 WriteChannelPort4 400040 => ch1[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 AHCI port 1 Base: 0xf773d180 MemIo 1 Proc 0 AHCI1_0x0 (0xf773d180) = 0x1e213000 AHCI1_0x4 (0xf773d184) = 0x0 AHCI1_0x8 (0xf773d188) = 0x1e213400 AHCI1_0xc (0xf773d18c) = 0x0 AHCI1_0x10 (0xf773d190) = 0x400040 AHCI1_0x14 (0xf773d194) = 0x0 AHCI1_0x18 (0xf773d198) = 0x40c017 AHCI1_0x1c (0xf773d19c) = 0x0 AHCI1_0x20 (0xf773d1a0) = 0x150 AHCI1_0x24 (0xf773d1a4) = 0x101 AHCI1_0x28 (0xf773d1a8) = 0x133 AHCI1_0x2c (0xf773d1ac) = 0x0 AHCI1_0x30 (0xf773d1b0) = 0x4050000 AHCI1_0x34 (0xf773d1b4) = 0x0 AHCI1_0x38 (0xf773d1b8) = 0x0 AHCI1_0x3c (0xf773d1bc) = 0x0 chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 6, 2 luns Chan 0xb7b394c0 Lun 0x0 Lun ptr 0xb7b3bc60 Lun 0x1 Lun ptr 0xb7b3bf78 AtaReq 0xb7b40000: cmd aligned b7b40080, d=20 ahci_cmd_ptr 0xb7b40080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b33000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b33000 AtapiVirtToPhysAddr_: b7b33000 -> 00000000:1e211000 AtapiDmaAlloc: CLP Phys BASE 1e211000 imp: 0x33 & 0x4 chan 2 not implemented chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 6, 2 luns Chan 0xb7b39720 Lun 0x0 Lun ptr 0xb7b3c290 Lun 0x1 Lun ptr 0xb7b3c5a8 AtaReq 0xb7b41000: cmd aligned b7b41080, d=20 ahci_cmd_ptr 0xb7b41080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b31000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b31000 AtapiVirtToPhysAddr_: b7b31000 -> 00000000:1e20f000 AtapiDmaAlloc: CLP Phys BASE 1e20f000 imp: 0x33 & 0x8 chan 3 not implemented chan 4, offs 0x300 AtapiSetupLunPtrs for channel 4 of 6, 2 luns Chan 0xb7b39980 Lun 0x0 Lun ptr 0xb7b3c8c0 Lun 0x1 Lun ptr 0xb7b3cbd8 AtaReq 0xb7b42000: cmd aligned b7b42080, d=20 ahci_cmd_ptr 0xb7b42080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b2f000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b2f000 AtapiVirtToPhysAddr_: b7b2f000 -> 00000000:1e20d000 AtapiDmaAlloc: CLP Phys BASE 1e20d000 imp: 0x33 & 0x10 UniataAhciResume: lChan 4 WriteChannelPort4 0 => ch4[14] AHCI CLB setup WriteChannelPort4 1e20d000 => ch4[0] WriteChannelPort4 0 => ch4[4] AHCI RCV FIS setup WriteChannelPort4 1e20d400 => ch4[8] WriteChannelPort4 0 => ch4[c] WriteChannelPort4 10000006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 400040 WriteChannelPort4 400040 => ch4[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 AHCI port 4 Base: 0xf773d300 MemIo 1 Proc 0 AHCI4_0x0 (0xf773d300) = 0x1e20d000 AHCI4_0x4 (0xf773d304) = 0x0 AHCI4_0x8 (0xf773d308) = 0x1e20d400 AHCI4_0xc (0xf773d30c) = 0x0 AHCI4_0x10 (0xf773d310) = 0x400040 AHCI4_0x14 (0xf773d314) = 0x0 AHCI4_0x18 (0xf773d318) = 0x40c017 AHCI4_0x1c (0xf773d31c) = 0x0 AHCI4_0x20 (0xf773d320) = 0x150 AHCI4_0x24 (0xf773d324) = 0x101 AHCI4_0x28 (0xf773d328) = 0x133 AHCI4_0x2c (0xf773d32c) = 0x0 AHCI4_0x30 (0xf773d330) = 0x4050000 AHCI4_0x34 (0xf773d334) = 0x0 AHCI4_0x38 (0xf773d338) = 0x0 AHCI4_0x3c (0xf773d33c) = 0x0 chan 5, offs 0x380 AtapiSetupLunPtrs for channel 5 of 6, 2 luns Chan 0xb7b39be0 Lun 0x0 Lun ptr 0xb7b3cef0 Lun 0x1 Lun ptr 0xb7b3d208 AtaReq 0xb7b43000: cmd aligned b7b43080, d=20 ahci_cmd_ptr 0xb7b43080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b2d000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b2d000 AtapiVirtToPhysAddr_: b7b2d000 -> 00000000:1e20b000 AtapiDmaAlloc: CLP Phys BASE 1e20b000 imp: 0x33 & 0x20 UniataAhciResume: lChan 5 WriteChannelPort4 0 => ch5[14] AHCI CLB setup WriteChannelPort4 1e20b000 => ch5[0] WriteChannelPort4 0 => ch5[4] AHCI RCV FIS setup WriteChannelPort4 1e20b400 => ch5[8] WriteChannelPort4 0 => ch5[c] WriteChannelPort4 10000006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 400040 WriteChannelPort4 400040 => ch5[10] SError 0x40d0000, IS 0x400040 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 AHCI port 5 Base: 0xf773d380 MemIo 1 Proc 0 AHCI5_0x0 (0xf773d380) = 0x1e20b000 AHCI5_0x4 (0xf773d384) = 0x0 AHCI5_0x8 (0xf773d388) = 0x1e20b400 AHCI5_0xc (0xf773d38c) = 0x0 AHCI5_0x10 (0xf773d390) = 0x400040 AHCI5_0x14 (0xf773d394) = 0x0 AHCI5_0x18 (0xf773d398) = 0x40c017 AHCI5_0x1c (0xf773d39c) = 0x0 AHCI5_0x20 (0xf773d3a0) = 0x150 AHCI5_0x24 (0xf773d3a4) = 0x101 AHCI5_0x28 (0xf773d3a8) = 0x123 AHCI5_0x2c (0xf773d3ac) = 0x0 AHCI5_0x30 (0xf773d3b0) = 0x40d0000 AHCI5_0x34 (0xf773d3b4) = 0x0 AHCI5_0x38 (0xf773d3b8) = 0x0 AHCI5_0x3c (0xf773d3bc) = 0x0 simplexOnly = 0 (2)!MasterDev patch irq line = 0xa update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 11, Level2 0, Vector 10, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x6, channel 0x0 de 0xb7b447dc, Channel 0x0 chan = 0xb7b39000 AtapiSetupLunPtrs for channel 0 of 6, 2 luns Chan 0xb7b39000 Lun 0x0 Lun ptr 0xb7b3b000 Lun 0x1 Lun ptr 0xb7b3b318 AtaReq 0xb7b3e000: cmd aligned b7b3e080, d=20 ahci_cmd_ptr 0xb7b3e080 AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773d120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773d128), Mem: AtapiDmaAlloc: AHCI already initialized b7b37000 de 0xb7b447dc, Channel 0x1 chan = 0xb7b39260 AtapiSetupLunPtrs for channel 1 of 6, 2 luns Chan 0xb7b39260 Lun 0x0 Lun ptr 0xb7b3b630 Lun 0x1 Lun ptr 0xb7b3b948 AtaReq 0xb7b3f000: cmd aligned b7b3f080, d=20 ahci_cmd_ptr 0xb7b3f080 AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan 1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773d1a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773d1a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b35000 de 0xb7b447dc, Channel 0x2 chan = 0xb7b394c0 AtapiSetupLunPtrs for channel 2 of 6, 2 luns Chan 0xb7b394c0 Lun 0x0 Lun ptr 0xb7b3bc60 Lun 0x1 Lun ptr 0xb7b3bf78 AtaReq 0xb7b40000: cmd aligned b7b40080, d=20 ahci_cmd_ptr 0xb7b40080 AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan 2 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773d220), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773d228), Mem: AtapiDmaAlloc: AHCI already initialized b7b33000 de 0xb7b447dc, Channel 0x3 chan = 0xb7b39720 AtapiSetupLunPtrs for channel 3 of 6, 2 luns Chan 0xb7b39720 Lun 0x0 Lun ptr 0xb7b3c290 Lun 0x1 Lun ptr 0xb7b3c5a8 AtaReq 0xb7b41000: cmd aligned b7b41080, d=20 ahci_cmd_ptr 0xb7b41080 AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan 3 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773d2a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773d2a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b31000 de 0xb7b447dc, Channel 0x4 chan = 0xb7b39980 AtapiSetupLunPtrs for channel 4 of 6, 2 luns Chan 0xb7b39980 Lun 0x0 Lun ptr 0xb7b3c8c0 Lun 0x1 Lun ptr 0xb7b3cbd8 AtaReq 0xb7b42000: cmd aligned b7b42080, d=20 ahci_cmd_ptr 0xb7b42080 AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan 4 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773d320), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773d328), Mem: AtapiDmaAlloc: AHCI already initialized b7b2f000 de 0xb7b447dc, Channel 0x5 chan = 0xb7b39be0 AtapiSetupLunPtrs for channel 5 of 6, 2 luns Chan 0xb7b39be0 Lun 0x0 Lun ptr 0xb7b3cef0 Lun 0x1 Lun ptr 0xb7b3d208 AtaReq 0xb7b43000: cmd aligned b7b43080, d=20 ahci_cmd_ptr 0xb7b43080 AtapiReadChipConfig: devExt 0xb7b447dc AtapiReadChipConfig: dev 0x1, ph chan 5 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773d3a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773d3a8), Mem: AtapiDmaAlloc: AHCI already initialized b7b2d000 exit: init spinlock MasterDev=0x0, NumberChannels=0x6, Isr2DevObj=0xb7de7d88 Init ISR: Multichannel native mode, go... Already initialized [1] 0xb7de7d88 MasterDev=0x0, NumberChannels=0x6, Isr2DevObj=0xb7de7d88 final chan[6] InterruptMode: 0, Level 11, Level2 0, Vector 10, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773d000 MemIo 1 Proc 0 AHCI_0x0 (0xf773d000) = 0xf737ff03 AHCI_0x4 (0xf773d004) = 0x80000002 AHCI_0x8 (0xf773d008) = 0x0 AHCI_0xc (0xf773d00c) = 0x33 AHCI_0x10 (0xf773d010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff03 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x33 AHCI PI mask 0x3f masked AHCI PI 0x33 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 6, 2 luns Chan 0xb7b39000 Lun 0x0 Lun ptr 0xb7b3b000 Lun 0x1 Lun ptr 0xb7b3b318 AtaReq 0xb7b3e000: cmd aligned b7b3e080, d=20 ahci_cmd_ptr 0xb7b3e080 AtapiDmaAlloc: AHCI already initialized b7b37000 imp: 0x33 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e215000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e215400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 400040 WriteChannelPort4 400040 => ch0[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 AHCI port 0 Base: 0xf773d100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773d100) = 0x1e215000 AHCI0_0x4 (0xf773d104) = 0x0 AHCI0_0x8 (0xf773d108) = 0x1e215400 AHCI0_0xc (0xf773d10c) = 0x0 AHCI0_0x10 (0xf773d110) = 0x400040 AHCI0_0x14 (0xf773d114) = 0x0 AHCI0_0x18 (0xf773d118) = 0x40c017 AHCI0_0x1c (0xf773d11c) = 0x0 AHCI0_0x20 (0xf773d120) = 0x150 AHCI0_0x24 (0xf773d124) = 0x101 AHCI0_0x28 (0xf773d128) = 0x133 AHCI0_0x2c (0xf773d12c) = 0x0 AHCI0_0x30 (0xf773d130) = 0x4050000 AHCI0_0x34 (0xf773d134) = 0x0 AHCI0_0x38 (0xf773d138) = 0x0 AHCI0_0x3c (0xf773d13c) = 0x0 chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 6, 2 luns Chan 0xb7b39260 Lun 0x0 Lun ptr 0xb7b3b630 Lun 0x1 Lun ptr 0xb7b3b948 AtaReq 0xb7b3f000: cmd aligned b7b3f080, d=20 ahci_cmd_ptr 0xb7b3f080 AtapiDmaAlloc: AHCI already initialized b7b35000 imp: 0x33 & 0x2 UniataAhciResume: lChan 1 WriteChannelPort4 0 => ch1[14] AHCI CLB setup WriteChannelPort4 1e213000 => ch1[0] WriteChannelPort4 0 => ch1[4] AHCI RCV FIS setup WriteChannelPort4 1e213400 => ch1[8] WriteChannelPort4 0 => ch1[c] WriteChannelPort4 10000006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 400040 WriteChannelPort4 400040 => ch1[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 AHCI port 1 Base: 0xf773d180 MemIo 1 Proc 0 AHCI1_0x0 (0xf773d180) = 0x1e213000 AHCI1_0x4 (0xf773d184) = 0x0 AHCI1_0x8 (0xf773d188) = 0x1e213400 AHCI1_0xc (0xf773d18c) = 0x0 AHCI1_0x10 (0xf773d190) = 0x400040 AHCI1_0x14 (0xf773d194) = 0x0 AHCI1_0x18 (0xf773d198) = 0x40c017 AHCI1_0x1c (0xf773d19c) = 0x0 AHCI1_0x20 (0xf773d1a0) = 0x150 AHCI1_0x24 (0xf773d1a4) = 0x101 AHCI1_0x28 (0xf773d1a8) = 0x133 AHCI1_0x2c (0xf773d1ac) = 0x0 AHCI1_0x30 (0xf773d1b0) = 0x4050000 AHCI1_0x34 (0xf773d1b4) = 0x0 AHCI1_0x38 (0xf773d1b8) = 0x0 AHCI1_0x3c (0xf773d1bc) = 0x0 chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 6, 2 luns Chan 0xb7b394c0 Lun 0x0 Lun ptr 0xb7b3bc60 Lun 0x1 Lun ptr 0xb7b3bf78 AtaReq 0xb7b40000: cmd aligned b7b40080, d=20 ahci_cmd_ptr 0xb7b40080 AtapiDmaAlloc: AHCI already initialized b7b33000 imp: 0x33 & 0x4 chan 2 not implemented chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 6, 2 luns Chan 0xb7b39720 Lun 0x0 Lun ptr 0xb7b3c290 Lun 0x1 Lun ptr 0xb7b3c5a8 AtaReq 0xb7b41000: cmd aligned b7b41080, d=20 ahci_cmd_ptr 0xb7b41080 AtapiDmaAlloc: AHCI already initialized b7b31000 imp: 0x33 & 0x8 chan 3 not implemented chan 4, offs 0x300 AtapiSetupLunPtrs for channel 4 of 6, 2 luns Chan 0xb7b39980 Lun 0x0 Lun ptr 0xb7b3c8c0 Lun 0x1 Lun ptr 0xb7b3cbd8 AtaReq 0xb7b42000: cmd aligned b7b42080, d=20 ahci_cmd_ptr 0xb7b42080 AtapiDmaAlloc: AHCI already initialized b7b2f000 imp: 0x33 & 0x10 UniataAhciResume: lChan 4 WriteChannelPort4 0 => ch4[14] AHCI CLB setup WriteChannelPort4 1e20d000 => ch4[0] WriteChannelPort4 0 => ch4[4] AHCI RCV FIS setup WriteChannelPort4 1e20d400 => ch4[8] WriteChannelPort4 0 => ch4[c] WriteChannelPort4 10000006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 400040 WriteChannelPort4 400040 => ch4[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 AHCI port 4 Base: 0xf773d300 MemIo 1 Proc 0 AHCI4_0x0 (0xf773d300) = 0x1e20d000 AHCI4_0x4 (0xf773d304) = 0x0 AHCI4_0x8 (0xf773d308) = 0x1e20d400 AHCI4_0xc (0xf773d30c) = 0x0 AHCI4_0x10 (0xf773d310) = 0x400040 AHCI4_0x14 (0xf773d314) = 0x0 AHCI4_0x18 (0xf773d318) = 0x40c017 AHCI4_0x1c (0xf773d31c) = 0x0 AHCI4_0x20 (0xf773d320) = 0x150 AHCI4_0x24 (0xf773d324) = 0x101 AHCI4_0x28 (0xf773d328) = 0x133 AHCI4_0x2c (0xf773d32c) = 0x0 AHCI4_0x30 (0xf773d330) = 0x4050000 AHCI4_0x34 (0xf773d334) = 0x0 AHCI4_0x38 (0xf773d338) = 0x0 AHCI4_0x3c (0xf773d33c) = 0x0 chan 5, offs 0x380 AtapiSetupLunPtrs for channel 5 of 6, 2 luns Chan 0xb7b39be0 Lun 0x0 Lun ptr 0xb7b3cef0 Lun 0x1 Lun ptr 0xb7b3d208 AtaReq 0xb7b43000: cmd aligned b7b43080, d=20 ahci_cmd_ptr 0xb7b43080 AtapiDmaAlloc: AHCI already initialized b7b2d000 imp: 0x33 & 0x20 UniataAhciResume: lChan 5 WriteChannelPort4 0 => ch5[14] AHCI CLB setup WriteChannelPort4 1e20b000 => ch5[0] WriteChannelPort4 0 => ch5[4] AHCI RCV FIS setup WriteChannelPort4 1e20b400 => ch5[8] WriteChannelPort4 0 => ch5[c] WriteChannelPort4 10000006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 400040 WriteChannelPort4 400040 => ch5[10] SError 0x40d0000, IS 0x400040 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 AHCI port 5 Base: 0xf773d380 MemIo 1 Proc 0 AHCI5_0x0 (0xf773d380) = 0x1e20b000 AHCI5_0x4 (0xf773d384) = 0x0 AHCI5_0x8 (0xf773d388) = 0x1e20b400 AHCI5_0xc (0xf773d38c) = 0x0 AHCI5_0x10 (0xf773d390) = 0x400040 AHCI5_0x14 (0xf773d394) = 0x0 AHCI5_0x18 (0xf773d398) = 0x40c017 AHCI5_0x1c (0xf773d39c) = 0x0 AHCI5_0x20 (0xf773d3a0) = 0x150 AHCI5_0x24 (0xf773d3a4) = 0x101 AHCI5_0x28 (0xf773d3a8) = 0x123 AHCI5_0x2c (0xf773d3ac) = 0x0 AHCI5_0x30 (0xf773d3b0) = 0x40d0000 AHCI5_0x34 (0xf773d3b4) = 0x0 AHCI5_0x38 (0xf773d3b8) = 0x0 AHCI5_0x3c (0xf773d3bc) = 0x0 imp: 0x33 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 40c017 WriteChannelPort4 40c016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 TFD 0x150 AHCI port 0 Base: 0xf773d100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773d100) = 0x1e215000 AHCI0_0x4 (0xf773d104) = 0x0 AHCI0_0x8 (0xf773d108) = 0x1e215400 AHCI0_0xc (0xf773d10c) = 0x0 AHCI0_0x10 (0xf773d110) = 0x0 AHCI0_0x14 (0xf773d114) = 0x0 AHCI0_0x18 (0xf773d118) = 0x404016 AHCI0_0x1c (0xf773d11c) = 0x0 AHCI0_0x20 (0xf773d120) = 0x150 AHCI0_0x24 (0xf773d124) = 0x101 AHCI0_0x28 (0xf773d128) = 0x133 AHCI0_0x2c (0xf773d12c) = 0x300 AHCI0_0x30 (0xf773d130) = 0x0 AHCI0_0x34 (0xf773d134) = 0x0 AHCI0_0x38 (0xf773d138) = 0x0 AHCI0_0x3c (0xf773d13c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 WriteChannelPort4 f900003f => ch0[14] check PM UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 40c017 WriteChannelPort4 40c016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 400006 WriteChannelPort4 40000e => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 404017 WriteChannelPort4 404016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 400006 WriteChannelPort4 40000e => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b44820, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de75f8, AtaReq 0xb7b3e000, CMD 0xb7b3e080 ph 0 AHCI setup FIS b7b3e080, ch 0, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b7b44820, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b7b3e080) AtapiVirtToPhysAddr_: b7b3e080 -> 00000000:1e21c080 get Phys(data[0]=b7b44820) AtapiVirtToPhysAddr_: b7b44820 -> 00000000:1e222820 set TERM ph data[0]=0:1e222820 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b3e000 AHCI AtaReq CMD 0xb7b3e080 (ph 0x1e21c080) prd_length 0x1, flags 0x5, base 1e21c080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 2 IS 0x2 WriteChannelPort4 2 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: DATA AUS08 0 FW: 0Q29 S/N: I22402003349 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 14c, CAPs 0x850e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 0/0 PhysLogSectorSize 0x4000, 0x100, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 1 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x7f0 UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1e4815 NativeNumOfSectors 0x773bd2b0 Update NumOfSectors to 0x773bd2b0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de75f8, AtaReq 0xb7b3e000, CMD 0xb7b3e080 ph 1e21c080 AHCI setup FIS b7b3e080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b3e000 AHCI AtaReq CMD 0xb7b3e080 (ph 0x1e21c080) prd_length 0x0, flags 0x5, base 1e21c080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x773bd2af 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1e4815 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=f240/80/fc Geometry: C 0xf240 (0xf240) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b3b000 S/N:ADATA_SU800_____________________________-2I4220003394________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de75f8, AtaReq 0xb7b3e000, CMD 0xb7b3e080 ph 1e21c080 AHCI setup FIS b7b3e080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b3e000 AHCI AtaReq CMD 0xb7b3e080 (ph 0x1e21c080) prd_length 0x0, flags 0x5, base 1e21c080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de75f8, AtaReq 0xb7b3e000, CMD 0xb7b3e080 ph 1e21c080 AHCI setup FIS b7b3e080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b3e000 AHCI AtaReq CMD 0xb7b3e080 (ph 0x1e21c080) prd_length 0x0, flags 0x5, base 1e21c080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de75f8, AtaReq 0xb7b3e000, CMD 0xb7b3e080 ph 1e21c080 AHCI setup FIS b7b3e080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b3e000 AHCI AtaReq CMD 0xb7b3e080 (ph 0x1e21c080) prd_length 0x0, flags 0x5, base 1e21c080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb7de75f8, AtaReq 0xb7b3e000, CMD 0xb7b3e080 ph 1e21c080 AHCI setup FIS b7b3e080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb7b3e000 AHCI AtaReq CMD 0xb7b3e080 (ph 0x1e21c080) prd_length 0x0, flags 0x5, base 1e21c080 ReadChannelPort4 ch0[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0x33 & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x49 mode imp: 0x33 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiHwInitialize: lChannel 0x0, dev 1 imp: 0x33 & 0x2 AtapiChipInit: dev 0xffffffff, ph chan 1, c 1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 1 WriteChannelPort4 0 => ch1[14] UniataAhciHardReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 40c017 WriteChannelPort4 40c016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 TFD 0x150 AHCI port 1 Base: 0xf773d180 MemIo 1 Proc 0 AHCI1_0x0 (0xf773d180) = 0x1e213000 AHCI1_0x4 (0xf773d184) = 0x0 AHCI1_0x8 (0xf773d188) = 0x1e213400 AHCI1_0xc (0xf773d18c) = 0x0 AHCI1_0x10 (0xf773d190) = 0x0 AHCI1_0x14 (0xf773d194) = 0x0 AHCI1_0x18 (0xf773d198) = 0x404016 AHCI1_0x1c (0xf773d19c) = 0x0 AHCI1_0x20 (0xf773d1a0) = 0x150 AHCI1_0x24 (0xf773d1a4) = 0x101 AHCI1_0x28 (0xf773d1a8) = 0x133 AHCI1_0x2c (0xf773d1ac) = 0x300 AHCI1_0x30 (0xf773d1b0) = 0x0 AHCI1_0x34 (0xf773d1b4) = 0x0 AHCI1_0x38 (0xf773d1b8) = 0x0 AHCI1_0x3c (0xf773d1bc) = 0x0 ReadChannelPort4 ch1[24] = 101 sig: 0x101 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 WriteChannelPort4 f900003f => ch1[14] check PM UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 40c017 WriteChannelPort4 40c016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 400006 WriteChannelPort4 40000e => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_1: 0 WriteChannelPort4 0 => ch1[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 404017 WriteChannelPort4 404016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 400006 WriteChannelPort4 40000e => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b44820, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7638, AtaReq 0xb7b3f000, CMD 0xb7b3f080 ph 0 AHCI setup FIS b7b3f080, ch 1, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b7b44820, count 200, lCh 1, dev 0 get Phys(AHCI_CMD=b7b3f080) AtapiVirtToPhysAddr_: b7b3f080 -> 00000000:1e21d080 get Phys(data[0]=b7b44820) AtapiVirtToPhysAddr_: b7b44820 -> 00000000:1e222820 set TERM ph data[0]=0:1e222820 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b3f000 AHCI AtaReq CMD 0xb7b3f080 (ph 0x1e21d080) prd_length 0x1, flags 0x5, base 1e21d080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 2 IS 0x2 WriteChannelPort4 2 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 IssueIdentify: Status after read words 0x50 Model: aSsmnu gSS D58 0VE O FW: ME0T S/N: 2SBRXNHB134025 Z Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 60 SATA support: 16c, CAPs 0x850e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 0/0 PhysLogSectorSize 0x4000, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 1 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x3fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0xec93d NativeNumOfSectors 0x3a386030 Update NumOfSectors to 0x3a386030 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7638, AtaReq 0xb7b3f000, CMD 0xb7b3f080 ph 1e21d080 AHCI setup FIS b7b3f080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b3f000 AHCI AtaReq CMD 0xb7b3f080 (ph 0x1e21d080) prd_length 0x0, flags 0x5, base 1e21d080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 NativeNumOfSectors 0x3a38602f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0xec93d Use GEOM_STD, CHS=ed81/ff/3f Geometry: C 0xed81 (0xed81) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b3b630 S/N:Samsung_SSD_850_EVO_500GB_______________-S2RBNXBH310452Z_____ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x2 AtapiEnableInterrupts_1: 1 WriteChannelPort4 fd4000ff => ch1[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x1, dev 0 AtapiDisableInterrupts_1: 0 WriteChannelPort4 0 => ch1[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7638, AtaReq 0xb7b3f000, CMD 0xb7b3f080 ph 1e21d080 AHCI setup FIS b7b3f080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b3f000 AHCI AtaReq CMD 0xb7b3f080 (ph 0x1e21d080) prd_length 0x0, flags 0x5, base 1e21d080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7638, AtaReq 0xb7b3f000, CMD 0xb7b3f080 ph 1e21d080 AHCI setup FIS b7b3f080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b3f000 AHCI AtaReq CMD 0xb7b3f080 (ph 0x1e21d080) prd_length 0x0, flags 0x5, base 1e21d080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7638, AtaReq 0xb7b3f000, CMD 0xb7b3f080 ph 1e21d080 AHCI setup FIS b7b3f080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b3f000 AHCI AtaReq CMD 0xb7b3f080 (ph 0x1e21d080) prd_length 0x0, flags 0x5, base 1e21d080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 1/0 AtapiDisableInterrupts_1: 1 WriteChannelPort4 0 => ch1[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb7de7638, AtaReq 0xb7b3f000, CMD 0xb7b3f080 ph 1e21d080 AHCI setup FIS b7b3f080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7b3f000 AHCI AtaReq CMD 0xb7b3f080 (ph 0x1e21d080) prd_length 0x0, flags 0x5, base 1e21d080 ReadChannelPort4 ch1[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 imp: 0x33 & 0x2 AtapiEnableInterrupts_1: 2 WriteChannelPort4 0 => ch1[14] Using 0x49 mode imp: 0x33 & 0x2 AtapiEnableInterrupts_1: 1 WriteChannelPort4 fd4000ff => ch1[14] AtapiHwInitialize: lChannel 0x1, dev 1 imp: 0x33 & 0x4 imp: 0x33 & 0x8 imp: 0x33 & 0x10 AtapiChipInit: dev 0xffffffff, ph chan 4, c 4 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 4 WriteChannelPort4 0 => ch4[14] UniataAhciHardReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 40c017 WriteChannelPort4 40c016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 TFD 0x150 AHCI port 4 Base: 0xf773d300 MemIo 1 Proc 0 AHCI4_0x0 (0xf773d300) = 0x1e20d000 AHCI4_0x4 (0xf773d304) = 0x0 AHCI4_0x8 (0xf773d308) = 0x1e20d400 AHCI4_0xc (0xf773d30c) = 0x0 AHCI4_0x10 (0xf773d310) = 0x0 AHCI4_0x14 (0xf773d314) = 0x0 AHCI4_0x18 (0xf773d318) = 0x404016 AHCI4_0x1c (0xf773d31c) = 0x0 AHCI4_0x20 (0xf773d320) = 0x150 AHCI4_0x24 (0xf773d324) = 0x101 AHCI4_0x28 (0xf773d328) = 0x133 AHCI4_0x2c (0xf773d32c) = 0x300 AHCI4_0x30 (0xf773d330) = 0x0 AHCI4_0x34 (0xf773d334) = 0x0 AHCI4_0x38 (0xf773d338) = 0x0 AHCI4_0x3c (0xf773d33c) = 0x0 ReadChannelPort4 ch4[24] = 101 sig: 0x101 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 WriteChannelPort4 f900003f => ch4[14] check PM UniataAhciSoftReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 40c017 WriteChannelPort4 40c016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 4 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 4 send CLO ReadChannelPort4 ch4[18] = 400006 WriteChannelPort4 40000e => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_4: 0 WriteChannelPort4 0 => ch4[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 404017 WriteChannelPort4 404016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 4 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 4 send CLO ReadChannelPort4 ch4[18] = 400006 WriteChannelPort4 40000e => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b44820, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 0 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b7b44820, count 200, lCh 4, dev 0 get Phys(AHCI_CMD=b7b42080) AtapiVirtToPhysAddr_: b7b42080 -> 00000000:1e220080 get Phys(data[0]=b7b44820) AtapiVirtToPhysAddr_: b7b44820 -> 00000000:1e222820 set TERM ph data[0]=0:1e222820 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x1, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 2 IS 0x2 WriteChannelPort4 2 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 IssueIdentify: Status after read words 0x50 Model: DW CDW012SX12-R4B10T FW: 300. S/N: W -DXW17CA439182 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 240 SATA support: 24c, CAPs 0xff0e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x6003, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 5400 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x3fe UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1d9265 NativeNumOfSectors 0x74706db0 Update NumOfSectors to 0x74706db0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 NativeNumOfSectors 0x74706daf 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1d9265 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=ec93/80/fc Geometry: C 0xec93 (0xec93) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7b3c8c0 S/N:WDC_WD10S21X-24R1BT0-SSHD-8GB___________-_____WD-WX71AC341928 IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x10 AtapiEnableInterrupts_4: 1 WriteChannelPort4 fd4000ff => ch4[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x4, dev 0 AtapiDisableInterrupts_4: 0 WriteChannelPort4 0 => ch4[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 4/0 AtapiDisableInterrupts_4: 1 WriteChannelPort4 0 => ch4[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x4 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 4 [0x0] Srb 0xb7de76f8, AtaReq 0xb7b42000, CMD 0xb7b42080 ph 1e220080 AHCI setup FIS b7b42080, ch 4, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 4, AtaReq 0xb7b42000 AHCI AtaReq CMD 0xb7b42080 (ph 0x1e220080) prd_length 0x0, flags 0x5, base 1e220080 ReadChannelPort4 ch4[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch4[38] No CMD START, already active ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 1 IS 0x1 WriteChannelPort4 1 => ch4[10] UniataAhciStatus(4-4): hIS 0x0 UniataAhciEndTransaction: lChan 4 ReadChannelPort4 ch4[20] = 50 TFD 0x50 ReadChannelPort4 ch4[34] = 0 ReadChannelPort4 ch4[38] = 0 imp: 0x33 & 0x10 AtapiEnableInterrupts_4: 2 WriteChannelPort4 0 => ch4[14] Using 0x49 mode imp: 0x33 & 0x10 AtapiEnableInterrupts_4: 1 WriteChannelPort4 fd4000ff => ch4[14] AtapiHwInitialize: lChannel 0x4, dev 1 imp: 0x33 & 0x20 AtapiChipInit: dev 0xffffffff, ph chan 5, c 5 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 5 WriteChannelPort4 0 => ch5[14] UniataAhciHardReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 40c017 WriteChannelPort4 40c016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 TFD 0x150 AHCI port 5 Base: 0xf773d380 MemIo 1 Proc 0 AHCI5_0x0 (0xf773d380) = 0x1e20b000 AHCI5_0x4 (0xf773d384) = 0x0 AHCI5_0x8 (0xf773d388) = 0x1e20b400 AHCI5_0xc (0xf773d38c) = 0x0 AHCI5_0x10 (0xf773d390) = 0x0 AHCI5_0x14 (0xf773d394) = 0x0 AHCI5_0x18 (0xf773d398) = 0x404016 AHCI5_0x1c (0xf773d39c) = 0x0 AHCI5_0x20 (0xf773d3a0) = 0x150 AHCI5_0x24 (0xf773d3a4) = 0x101 AHCI5_0x28 (0xf773d3a8) = 0x123 AHCI5_0x2c (0xf773d3ac) = 0x300 AHCI5_0x30 (0xf773d3b0) = 0x0 AHCI5_0x34 (0xf773d3b4) = 0x0 AHCI5_0x38 (0xf773d3b8) = 0x0 AHCI5_0x3c (0xf773d3bc) = 0x0 ReadChannelPort4 ch5[24] = 101 sig: 0x101 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 WriteChannelPort4 f900003f => ch5[14] check PM UniataAhciSoftReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 40c017 WriteChannelPort4 40c016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 5 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 5 send CLO ReadChannelPort4 ch5[18] = 400006 WriteChannelPort4 40000e => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_5: 0 WriteChannelPort4 0 => ch5[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 404017 WriteChannelPort4 404016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 5 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 5 send CLO ReadChannelPort4 ch5[18] = 400006 WriteChannelPort4 40000e => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7b44820, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 0 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7b44820, count 200, lCh 5, dev 0 get Phys(AHCI_CMD=b7b43080) AtapiVirtToPhysAddr_: b7b43080 -> 00000000:1e221080 get Phys(data[0]=b7b44820) AtapiVirtToPhysAddr_: b7b44820 -> 00000000:1e222820 set TERM ph data[0]=0:1e222820 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x1, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 2 IS 0x2 WriteChannelPort4 2 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 IssueIdentify: Status after read words 0x50 Model: OTHSBI AQM10BA1D00 FW: XA00 S/N: 2 43F6S6SA Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/3f SATA: 40 SATA support: 4c, CAPs 0xf06 OrigTransferMode: 48, Active: 48 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x6003, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 5400 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1f8 UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1d9265 NativeNumOfSectors 0x74706db0 Update NumOfSectors to 0x74706db0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x1:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 1e221080 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x0, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 NativeNumOfSectors 0x74706daf 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1d9265 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=ec93/80/fc Geometry: C 0xec93 (0xec93) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) InitBadBlocks local LunExt 0xb7b3cef0 S/N:TOSHIBA_MQ01ABD100______________________-___________2346F6SAS IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0x33 & 0x20 AtapiEnableInterrupts_5: 1 WriteChannelPort4 fd4000ff => ch5[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x5, dev 0 AtapiDisableInterrupts_5: 0 WriteChannelPort4 0 => ch5[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 1e221080 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x0, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 1e221080 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x0, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 1e221080 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x0, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 1e221080 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x0, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x5 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 5/0 AtapiDisableInterrupts_5: 1 WriteChannelPort4 0 => ch5[14] UniataAhciSendPIOCommand: cntrlr 0x1:0x5 dev 0x0, cmd 0xef, lba 0x0 bcount 0x45 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 5 [0x0] Srb 0xb7de7738, AtaReq 0xb7b43000, CMD 0xb7b43080 ph 1e221080 AHCI setup FIS b7b43080, ch 5, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 5, AtaReq 0xb7b43000 AHCI AtaReq CMD 0xb7b43080 (ph 0x1e221080) prd_length 0x0, flags 0x5, base 1e221080 ReadChannelPort4 ch5[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch5[38] No CMD START, already active ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 1 IS 0x1 WriteChannelPort4 1 => ch5[10] UniataAhciStatus(5-5): hIS 0x0 UniataAhciEndTransaction: lChan 5 ReadChannelPort4 ch5[20] = 50 TFD 0x50 ReadChannelPort4 ch5[34] = 0 ReadChannelPort4 ch5[38] = 0 imp: 0x33 & 0x20 AtapiEnableInterrupts_5: 2 WriteChannelPort4 0 => ch5[14] Using 0x48 mode imp: 0x33 & 0x20 AtapiEnableInterrupts_5: 1 WriteChannelPort4 fd4000ff => ch5[14] AtapiHwInitialize: lChannel 0x5, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x1 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b1c000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b1c000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b39000, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39000, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39000, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 404017 WriteChannelPort4 404016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 400006 WriteChannelPort4 40000e => ch0[18] ReadChannelPort4 ch0[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch0[18] ReadChannelPort4 ch0[18] = 404016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch0[18] ReadChannelPort4 ch0[18] = 40c017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b39000, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39000, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39000, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x2 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b1c000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b1c000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x1:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b39260, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39260, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39260, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 404017 WriteChannelPort4 404016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 400006 WriteChannelPort4 40000e => ch1[18] ReadChannelPort4 ch1[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch1[18] ReadChannelPort4 ch1[18] = 404016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch1[18] ReadChannelPort4 ch1[18] = 40c017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b39260, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39260, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39260, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b394c0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b394c0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b394c0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b394c0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b394c0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b394c0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x8 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b39720, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39720, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39720, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x8 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b39720, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39720, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39720, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x10 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b1c000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b1c000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x4:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b39980, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39980, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39980, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x4:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x10 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch4[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 4 UniataAhciStop: lChan 4 ReadChannelPort4 ch4[18] = 404017 WriteChannelPort4 404016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 4 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 4 send CLO ReadChannelPort4 ch4[18] = 400006 WriteChannelPort4 40000e => ch4[18] ReadChannelPort4 ch4[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 4 ReadChannelPort4 ch4[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch4[18] ReadChannelPort4 ch4[18] = 404016 UniataAhciStart: lChan 4 ReadChannelPort4 ch4[10] = 0 WriteChannelPort4 0 => ch4[10] SError 0x0, IS 0x0 ReadChannelPort4 ch4[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch4[18] ReadChannelPort4 ch4[18] = 40c017 UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciSendCommand: lChan 4 WriteChannelPort4 1 => ch4[38] ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 1 ReadChannelPort4 ch4[10] = 0 ReadChannelPort4 ch4[38] = 0 CI 0x0 ReadChannelPort4 ch4[10] = 0 IS 0x0 WriteChannelPort4 0 => ch4[10] UniataAhciWaitReady: lChan 4 ReadChannelPort4 ch4[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b39980, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39980, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39980, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x5:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x20 SRB 0xf77b0200, CDB 0xf77b0230, AtaReq 0xb7b1c000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77afee8 ** Ide: Command AtaReq 0xb7b1c000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x5:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7b39be0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39be0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39be0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x5:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x5:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x33 & 0x20 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b1c000 SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 123 AHCI check ReadChannelPort4 ch5[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 5 UniataAhciStop: lChan 5 ReadChannelPort4 ch5[18] = 404017 WriteChannelPort4 404016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 5 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 5 send CLO ReadChannelPort4 ch5[18] = 400006 WriteChannelPort4 40000e => ch5[18] ReadChannelPort4 ch5[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 5 ReadChannelPort4 ch5[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch5[18] ReadChannelPort4 ch5[18] = 404016 UniataAhciStart: lChan 5 ReadChannelPort4 ch5[10] = 0 WriteChannelPort4 0 => ch5[10] SError 0x0, IS 0x0 ReadChannelPort4 ch5[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch5[18] ReadChannelPort4 ch5[18] = 40c017 UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciSendCommand: lChan 5 WriteChannelPort4 1 => ch5[38] ReadChannelPort4 ch5[38] = 1 ReadChannelPort4 ch5[10] = 0 ReadChannelPort4 ch5[38] = 0 CI 0x0 ReadChannelPort4 ch5[10] = 0 IS 0x0 WriteChannelPort4 0 => ch5[10] UniataAhciWaitReady: lChan 5 ReadChannelPort4 ch5[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b39be0, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b39be0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b39be0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x6:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x6:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x6:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request ScsiPortInitialize Status 0x0 Try init 1022 7901 (hal/halx86/legacy/bussupp.c:1274) Slot assignment for 5 on bus 6 (hal/halx86/legacy/bus/pcibus.c:742) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=2, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0x6 slotNumber=0x40 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf773c000 MemIo AHCI Base: 0xf773c000 MemIo 1 Proc 0 AHCI_0x0 (0xf773c000) = 0xf737ff00 AHCI_0x4 (0xf773c004) = 0x80000000 AHCI_0x8 (0xf773c008) = 0x0 AHCI_0xc (0xf773c00c) = 0x1 AHCI_0x10 (0xf773c010) = 0x10301 check AHCI mode, GHC 0x80000000 AHCI CAP 0xf737ff00, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0x1 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 CommandSlots 31 Detected Channels 1 / 1 Adjusted Channels 1 AHCI version 1.31 controller with 1 ports (mask 0x1) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf773c000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 PortMask 0x1 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 mask -> 1 chans Parameter NumberChannels Parameter NumberChannels = 0x1 reg -> 1 chans Final PortMask 0x1 allocate 2 Luns for 1 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb7b172b4 AtapiReadChipConfig: dev 0x2, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x2, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773c000 MemIo 1 Proc 0 AHCI_0x0 (0xf773c000) = 0xf737ff00 AHCI_0x4 (0xf773c004) = 0x80000000 AHCI_0x8 (0xf773c008) = 0x0 AHCI_0xc (0xf773c00c) = 0x1 AHCI_0x10 (0xf773c010) = 0x10301 get GHC disable intr, GHC 0x80000000 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff00 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x1 AHCI PI mask 0x1 masked AHCI PI 0x1 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7b17b40 Lun 0x0 Lun ptr 0xb7b15008 Lun 0x1 Lun ptr 0xb7b15320 AtaReq 0xb7b16000: cmd aligned b7b16080, d=20 ahci_cmd_ptr 0xb7b16080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7b13000 AtapiDmaAlloc: CLP BASE 1k-aligned b7b13000 AtapiVirtToPhysAddr_: b7b13000 -> 00000000:1e1f1000 AtapiDmaAlloc: CLP Phys BASE 1e1f1000 imp: 0x1 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e1f1000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e1f1400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 402016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 402016 CMD 0x402016 WriteChannelPort4 402017 => ch0[18] ReadChannelPort4 ch0[18] = 402017 AHCI port 0 Base: 0xf773c100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773c100) = 0x1e1f1000 AHCI0_0x4 (0xf773c104) = 0x0 AHCI0_0x8 (0xf773c108) = 0x1e1f1400 AHCI0_0xc (0xf773c10c) = 0x0 AHCI0_0x10 (0xf773c110) = 0x0 AHCI0_0x14 (0xf773c114) = 0x0 AHCI0_0x18 (0xf773c118) = 0x402017 AHCI0_0x1c (0xf773c11c) = 0x0 AHCI0_0x20 (0xf773c120) = 0x7f AHCI0_0x24 (0xf773c124) = 0xffffffff AHCI0_0x28 (0xf773c128) = 0x0 AHCI0_0x2c (0xf773c12c) = 0x0 AHCI0_0x30 (0xf773c130) = 0x0 AHCI0_0x34 (0xf773c134) = 0x0 AHCI0_0x38 (0xf773c138) = 0x0 AHCI0_0x3c (0xf773c13c) = 0x0 simplexOnly = 0 (2)!MasterDev patch irq line = 0xb update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 10, Level2 0, Vector 11, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x1, channel 0x0 de 0xb7b172b4, Channel 0x0 chan = 0xb7b17b40 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7b17b40 Lun 0x0 Lun ptr 0xb7b15008 Lun 0x1 Lun ptr 0xb7b15320 AtaReq 0xb7b16000: cmd aligned b7b16080, d=20 ahci_cmd_ptr 0xb7b16080 AtapiReadChipConfig: devExt 0xb7b172b4 AtapiReadChipConfig: dev 0x2, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773c120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773c128), Mem: AtapiDmaAlloc: AHCI already initialized b7b13000 exit: init spinlock MasterDev=0x0, NumberChannels=0x1, Isr2DevObj=0x0 Init ISR: Unnecessary MasterDev=0x0, NumberChannels=0x1, Isr2DevObj=0x0 final chan[1] InterruptMode: 0, Level 10, Level2 0, Vector 11, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773c000 MemIo 1 Proc 0 AHCI_0x0 (0xf773c000) = 0xf737ff00 AHCI_0x4 (0xf773c004) = 0x80000002 AHCI_0x8 (0xf773c008) = 0x0 AHCI_0xc (0xf773c00c) = 0x1 AHCI_0x10 (0xf773c010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff00 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x1 AHCI PI mask 0x1 masked AHCI PI 0x1 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7b17b40 Lun 0x0 Lun ptr 0xb7b15008 Lun 0x1 Lun ptr 0xb7b15320 AtaReq 0xb7b16000: cmd aligned b7b16080, d=20 ahci_cmd_ptr 0xb7b16080 AtapiDmaAlloc: AHCI already initialized b7b13000 imp: 0x1 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e1f1000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e1f1400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 402016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 402016 CMD 0x402016 WriteChannelPort4 402017 => ch0[18] ReadChannelPort4 ch0[18] = 402017 AHCI port 0 Base: 0xf773c100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773c100) = 0x1e1f1000 AHCI0_0x4 (0xf773c104) = 0x0 AHCI0_0x8 (0xf773c108) = 0x1e1f1400 AHCI0_0xc (0xf773c10c) = 0x0 AHCI0_0x10 (0xf773c110) = 0x0 AHCI0_0x14 (0xf773c114) = 0x0 AHCI0_0x18 (0xf773c118) = 0x402017 AHCI0_0x1c (0xf773c11c) = 0x0 AHCI0_0x20 (0xf773c120) = 0x7f AHCI0_0x24 (0xf773c124) = 0xffffffff AHCI0_0x28 (0xf773c128) = 0x0 AHCI0_0x2c (0xf773c12c) = 0x0 AHCI0_0x30 (0xf773c130) = 0x0 AHCI0_0x34 (0xf773c134) = 0x0 AHCI0_0x38 (0xf773c138) = 0x0 AHCI0_0x3c (0xf773c13c) = 0x0 imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 402017 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 402016 final CMD 0x402016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: UniataSataConnect: SStatus 00000000 no PHY No devices in all LUNs WriteChannelPort4 80400040 => ch0[14] FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 0 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiHwInitialize: lChannel 0x0, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x1 & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b02000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b17b40, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b17b40, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b17b40, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x1 & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7b02000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b17b40, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b17b40, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b17b40, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request (hal/halx86/legacy/bussupp.c:1274) Slot assignment for 5 on bus 10 (hal/halx86/legacy/bus/pcibus.c:742) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=2, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0xa slotNumber=0x40 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf773b000 MemIo AHCI Base: 0xf773b000 MemIo 1 Proc 0 AHCI_0x0 (0xf773b000) = 0xf737ff00 AHCI_0x4 (0xf773b004) = 0x80000002 AHCI_0x8 (0xf773b008) = 0x0 AHCI_0xc (0xf773b00c) = 0x1 AHCI_0x10 (0xf773b010) = 0x10301 check AHCI mode, GHC 0x80000002 AHCI CAP 0xf737ff00, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0x1 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 CommandSlots 31 Detected Channels 1 / 1 Adjusted Channels 1 AHCI version 1.31 controller with 1 ports (mask 0x1) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf773b000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 PortMask 0x1 Parameter PortMask Parameter PortMask = 0x1 Force PortMask 0x1 mask -> 1 chans Parameter NumberChannels Parameter NumberChannels = 0x1 reg -> 1 chans Final PortMask 0x1 allocate 2 Luns for 1 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb7affcec AtapiReadChipConfig: dev 0x2, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x2, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773b000 MemIo 1 Proc 0 AHCI_0x0 (0xf773b000) = 0xf737ff00 AHCI_0x4 (0xf773b004) = 0x80000002 AHCI_0x8 (0xf773b008) = 0x0 AHCI_0xc (0xf773b00c) = 0x1 AHCI_0x10 (0xf773b010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff00 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x1 AHCI PI mask 0x1 masked AHCI PI 0x1 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7b17678 Lun 0x0 Lun ptr 0xb7afd008 Lun 0x1 Lun ptr 0xb7afd320 AtaReq 0xb7afe000: cmd aligned b7afe080, d=20 ahci_cmd_ptr 0xb7afe080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7afb000 AtapiDmaAlloc: CLP BASE 1k-aligned b7afb000 AtapiVirtToPhysAddr_: b7afb000 -> 00000000:1e1d9000 AtapiDmaAlloc: CLP Phys BASE 1e1d9000 imp: 0x1 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e1d9000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e1d9400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 402016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 402016 CMD 0x402016 WriteChannelPort4 402017 => ch0[18] ReadChannelPort4 ch0[18] = 402017 AHCI port 0 Base: 0xf773b100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773b100) = 0x1e1d9000 AHCI0_0x4 (0xf773b104) = 0x0 AHCI0_0x8 (0xf773b108) = 0x1e1d9400 AHCI0_0xc (0xf773b10c) = 0x0 AHCI0_0x10 (0xf773b110) = 0x0 AHCI0_0x14 (0xf773b114) = 0x0 AHCI0_0x18 (0xf773b118) = 0x402017 AHCI0_0x1c (0xf773b11c) = 0x0 AHCI0_0x20 (0xf773b120) = 0x7f AHCI0_0x24 (0xf773b124) = 0xffffffff AHCI0_0x28 (0xf773b128) = 0x0 AHCI0_0x2c (0xf773b12c) = 0x0 AHCI0_0x30 (0xf773b130) = 0x0 AHCI0_0x34 (0xf773b134) = 0x0 AHCI0_0x38 (0xf773b138) = 0x0 AHCI0_0x3c (0xf773b13c) = 0x0 simplexOnly = 0 (2)!MasterDev update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 11, Level2 0, Vector 11, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x1, channel 0x0 de 0xb7affcec, Channel 0x0 chan = 0xb7b17678 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7b17678 Lun 0x0 Lun ptr 0xb7afd008 Lun 0x1 Lun ptr 0xb7afd320 AtaReq 0xb7afe000: cmd aligned b7afe080, d=20 ahci_cmd_ptr 0xb7afe080 AtapiReadChipConfig: devExt 0xb7affcec AtapiReadChipConfig: dev 0x2, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf773b120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf773b128), Mem: AtapiDmaAlloc: AHCI already initialized b7afb000 exit: init spinlock MasterDev=0x0, NumberChannels=0x1, Isr2DevObj=0x0 Init ISR: Unnecessary MasterDev=0x0, NumberChannels=0x1, Isr2DevObj=0x0 final chan[1] InterruptMode: 0, Level 11, Level2 0, Vector 11, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf773b000 MemIo 1 Proc 0 AHCI_0x0 (0xf773b000) = 0xf737ff00 AHCI_0x4 (0xf773b004) = 0x80000002 AHCI_0x8 (0xf773b008) = 0x0 AHCI_0xc (0xf773b00c) = 0x1 AHCI_0x10 (0xf773b010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff00 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0x1 AHCI PI mask 0x1 masked AHCI PI 0x1 SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7b17678 Lun 0x0 Lun ptr 0xb7afd008 Lun 0x1 Lun ptr 0xb7afd320 AtaReq 0xb7afe000: cmd aligned b7afe080, d=20 ahci_cmd_ptr 0xb7afe080 AtapiDmaAlloc: AHCI already initialized b7afb000 imp: 0x1 & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 1e1d9000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 1e1d9400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 402016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 402016 CMD 0x402016 WriteChannelPort4 402017 => ch0[18] ReadChannelPort4 ch0[18] = 402017 AHCI port 0 Base: 0xf773b100 MemIo 1 Proc 0 AHCI0_0x0 (0xf773b100) = 0x1e1d9000 AHCI0_0x4 (0xf773b104) = 0x0 AHCI0_0x8 (0xf773b108) = 0x1e1d9400 AHCI0_0xc (0xf773b10c) = 0x0 AHCI0_0x10 (0xf773b110) = 0x0 AHCI0_0x14 (0xf773b114) = 0x0 AHCI0_0x18 (0xf773b118) = 0x402017 AHCI0_0x1c (0xf773b11c) = 0x0 AHCI0_0x20 (0xf773b120) = 0x7f AHCI0_0x24 (0xf773b124) = 0xffffffff AHCI0_0x28 (0xf773b128) = 0x0 AHCI0_0x2c (0xf773b12c) = 0x0 AHCI0_0x30 (0xf773b130) = 0x0 AHCI0_0x34 (0xf773b134) = 0x0 AHCI0_0x38 (0xf773b138) = 0x0 AHCI0_0x3c (0xf773b13c) = 0x0 imp: 0x1 & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 402017 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 402016 final CMD 0x402016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: UniataSataConnect: SStatus 00000000 no PHY No devices in all LUNs WriteChannelPort4 80400040 => ch0[14] FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy imp: 0x1 & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 0 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiHwInitialize: lChannel 0x0, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x1 & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7aea000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b17678, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b17678, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b17678, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0x1 & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf77b0200 TopLevel (3), AtaReq 0xb7aea000 SStatus 0 SATA DET <= SStatus_DET_Dev_NoPhy AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7b17678, f77b0200) AtapiStartIo: UniataRemoveRequest(b7b17678, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7b17678, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: Communication port INQUIRY AtapiStartIo: Srb 0xf77b0200 complete with status 0x1 AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b0200 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f77b0200) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request ScsiPortInitialize Status 0x0 Parameter IgnoreIsa Parameter IgnoreIsa = 0x0 ATAPI IDE: Look for ISA Controllers AtapiFindIsaController (ISA): assume max PIO4 allocate 2 Luns for 1 channels AtapiSetupLunPtrs for channel 0 of 1, 2 luns Chan 0xb7ae7b40 Lun 0x0 Lun ptr 0xb7ae6008 Lun 0x1 Lun ptr 0xb7ae6320 AtapiReadChipConfig: devExt 0xb7ae72b4 AtapiReadChipConfig: dev 0xffffffff, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0xc Parameter MaxTransferMode Parameter MaxTransferMode = 0xc MaxTransferMode (overriden): 0xc Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x0 VendorID/DeviceID/Rev 0x0/0x0/0x0 AtapiFindIsaController: adapterCount=0 portBase[0]=1f0 Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 BaseIoAddress1=1f0 BaseIoAddress2=3f6 expected InterruptLevel=e AltStatus (0xff) Reg_0x1 (0x1f1) = 0xff Reg_0x2 (0x1f2) = 0xff Reg_0x3 (0x1f3) = 0xff Reg_0x4 (0x1f4) = 0xff Reg_0x5 (0x1f5) = 0xff Reg_0x6 (0x1f6) = 0xff Reg_0x7 (0x1f7) = 0xff AtapiFindIsaController: Identifier read back from Master (0xff) AtapiFindIsaController: Identifier read back from Slave (0xff) AtapiFindIsaController: cleanup AccessRanges 0 AtapiFindIsaController: cleanup AccessRanges 1 AtapiFindIsaController: adapterCount=1 portBase[1]=170 Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 BaseIoAddress1=170 BaseIoAddress2=376 expected InterruptLevel=f AltStatus (0xff) Reg_0x1 (0x171) = 0xff Reg_0x2 (0x172) = 0xff Reg_0x3 (0x173) = 0xff Reg_0x4 (0x174) = 0xff Reg_0x5 (0x175) = 0xff Reg_0x6 (0x176) = 0xff Reg_0x7 (0x177) = 0xff AtapiFindIsaController: Identifier read back from Master (0xff) AtapiFindIsaController: Identifier read back from Slave (0xff) AtapiFindIsaController: cleanup AccessRanges 0 AtapiFindIsaController: cleanup AccessRanges 1 AtapiFindIsaController: adapterCount=2 portBase[2]=1e8 Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 BaseIoAddress1=1e8 BaseIoAddress2=3ee expected InterruptLevel=b AltStatus (0xff) Reg_0x1 (0x1e9) = 0xff Reg_0x2 (0x1ea) = 0xff Reg_0x3 (0x1eb) = 0xff Reg_0x4 (0x1ec) = 0xff Reg_0x5 (0x1ed) = 0xff Reg_0x6 (0x1ee) = 0xff Reg_0x7 (0x1ef) = 0xff AtapiFindIsaController: Identifier read back from Master (0xff) AtapiFindIsaController: Identifier read back from Slave (0xff) AtapiFindIsaController: cleanup AccessRanges 0 AtapiFindIsaController: cleanup AccessRanges 1 AtapiFindIsaController: adapterCount=3 portBase[3]=168 Parameter PortBase Parameter PortBase = 0x0 Parameter Irq Parameter Irq = 0x0 BaseIoAddress1=168 BaseIoAddress2=36e expected InterruptLevel=a AltStatus (0xff) Reg_0x1 (0x169) = 0xff Reg_0x2 (0x16a) = 0xff Reg_0x3 (0x16b) = 0xff Reg_0x4 (0x16c) = 0xff Reg_0x5 (0x16d) = 0xff Reg_0x6 (0x16e) = 0xff Reg_0x7 (0x16f) = 0xff AtapiFindIsaController: Identifier read back from Master (0xff) AtapiFindIsaController: Identifier read back from Slave (0xff) AtapiFindIsaController: cleanup AccessRanges 0 AtapiFindIsaController: cleanup AccessRanges 1 AtapiFindIsaController: return SP_RETURN_NOT_FOUND ScsiPortInitialize Status 0xc00000c0 Parameter IgnoreMca Parameter IgnoreMca = 0x0 ATAPI IDE: Look for MCA Controllers ScsiPortInitialize Status 0xc00000c0 Leave UNIATA MiniPort DriverEntry with status 0x0 (ntoskrnl/io/iomgr/driver.c:1635) '\Driver\BUSLOGIC' initialization failed, status (0xc00000c0) (ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\BUSLOGIC' (ntoskrnl/io/iomgr/driver.c:1635) '\Driver\CDROM' initialization failed, status (0xc000000e) (ntoskrnl/io/iomgr/driver.c:64) Deleting driver object '\Driver\CDROM' TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xf77b0530, CDB 0xf77b0560, AtaReq 0xb7dec000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf77b0530 TopLevel (3), AtaReq 0xb7dec000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77b0298 ** Ide: Command AtaReq 0xb7dec000 ** --- ** ** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x3:0x0:0x0 ** IDE disk 0x0 - #sectors 0x3f, #heads 0xff, #cylinders 0x76c1 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0530 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7e01728, f77b0530) AtapiStartIo: UniataRemoveRequest(b7e01728, f77b0530) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7dec000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7dec000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77b0168 ** Ide: Command AtaReq 0xb7dec000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb7dec000: cmd aligned b7dec080, d=20 ahci_cmd_ptr 0xb7dec080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7dec080) AtapiVirtToPhysAddr_: b7dec080 -> 00000000:1e4ca080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c4000 set TERM ph data[0]=0:1e1c4000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7dec080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7dec000 AHCI AtaReq CMD 0xb7dec080 (ph 0x1e4ca080) prd_length 0x1, flags 0x5, base 1e4ca080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7e01728, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7e01728 senseBuffer 0xb7ded000, chan 0xb7e01728, ReqFlags 0xe AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 0 do nothing chan 0xb7e01728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf7740280 MemIo 1 Proc 0 AHCI3_0x0 (0xf7740280) = 0x1e261000 AHCI3_0x4 (0xf7740284) = 0x0 AHCI3_0x8 (0xf7740288) = 0x1e261400 AHCI3_0xc (0xf774028c) = 0x0 AHCI3_0x10 (0xf7740290) = 0x0 AHCI3_0x14 (0xf7740294) = 0xfd4000ff AHCI3_0x18 (0xf7740298) = 0x40c017 AHCI3_0x1c (0xf774029c) = 0x0 AHCI3_0x20 (0xf77402a0) = 0x1d0 AHCI3_0x24 (0xf77402a4) = 0x101 AHCI3_0x28 (0xf77402a8) = 0x123 AHCI3_0x2c (0xf77402ac) = 0x300 AHCI3_0x30 (0xf77402b0) = 0x0 AHCI3_0x34 (0xf77402b4) = 0x0 AHCI3_0x38 (0xf77402b8) = 0x1 AHCI3_0x3c (0xf77402bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf7740280 MemIo 1 Proc 0 AHCI3_0x0 (0xf7740280) = 0x1e261000 AHCI3_0x4 (0xf7740284) = 0x0 AHCI3_0x8 (0xf7740288) = 0x1e261400 AHCI3_0xc (0xf774028c) = 0x0 AHCI3_0x10 (0xf7740290) = 0x0 AHCI3_0x14 (0xf7740294) = 0x0 AHCI3_0x18 (0xf7740298) = 0x404016 AHCI3_0x1c (0xf774029c) = 0x0 AHCI3_0x20 (0xf77402a0) = 0x150 AHCI3_0x24 (0xf77402a4) = 0x101 AHCI3_0x28 (0xf77402a8) = 0x123 AHCI3_0x2c (0xf77402ac) = 0x300 AHCI3_0x30 (0xf77402b0) = 0x0 AHCI3_0x34 (0xf77402b4) = 0x0 AHCI3_0x38 (0xf77402b8) = 0x0 AHCI3_0x3c (0xf77402bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 CI 0x1 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] AHCI: timeout, SError 0x0 ReadChannelPort4 ch3[20] = 1d0 TFD 0x1d0 timeout re-check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 CI 0x1 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] AHCI: timeout, SError 0x0 ReadChannelPort4 ch3[20] = 1d0 TFD 0x1d0 timeout signature 0xffffffff default to ATA ??? process connected devices 0 - 1 Chan 0xb7e01728 Lun 0x0 Lun ptr 0xb7b97290 found some device IssueIdentify: Checking for IDE. Status (0xd0) IssueIdentify: statusByte != IDE_STATUS_IDLE IssueIdentify: no dev (dev 0) identify failed ! Chan 0xb7e01728 Lun 0x1 Lun ptr 0xb7b975a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf7740280 MemIo 1 Proc 0 AHCI3_0x0 (0xf7740280) = 0x1e261000 AHCI3_0x4 (0xf7740284) = 0x0 AHCI3_0x8 (0xf7740288) = 0x1e261400 AHCI3_0xc (0xf774028c) = 0x0 AHCI3_0x10 (0xf7740290) = 0x0 AHCI3_0x14 (0xf7740294) = 0x0 AHCI3_0x18 (0xf7740298) = 0x404016 AHCI3_0x1c (0xf774029c) = 0x0 AHCI3_0x20 (0xf77402a0) = 0x150 AHCI3_0x24 (0xf77402a4) = 0x101 AHCI3_0x28 (0xf77402a8) = 0x123 AHCI3_0x2c (0xf77402ac) = 0x300 AHCI3_0x30 (0xf77402b0) = 0x0 AHCI3_0x34 (0xf77402b4) = 0x0 AHCI3_0x38 (0xf77402b8) = 0x0 AHCI3_0x3c (0xf77402bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 CI 0x1 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] AHCI: timeout, SError 0x0 ReadChannelPort4 ch3[20] = 1d0 TFD 0x1d0 timeout re-check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 CI 0x1 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] AHCI: timeout, SError 0x0 ReadChannelPort4 ch3[20] = 1d0 TFD 0x1d0 timeout signature 0xffffffff default to ATA ??? FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 CI 0x1 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] AHCI: timeout, SError 0x0 ReadChannelPort4 ch3[20] = 1d0 TFD 0x1d0 timeout CheckDevice: (no dev) imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 0 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiHwInitialize: lChannel 0x3, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 AtapiStartIo: EXECUTE_SCSI rejected (2) SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xb7b18520 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01728, b7b18520) AtapiStartIo: UniataRemoveRequest(b7e01728, b7b18520) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 AtapiStartIo: EXECUTE_SCSI rejected (2) SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xb7b18520 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01728, b7b18520) AtapiStartIo: UniataRemoveRequest(b7e01728, b7b18520) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 AtapiStartIo: EXECUTE_SCSI rejected (2) SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf77b01b0 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b7e01728, f77b01b0) AtapiStartIo: UniataRemoveRequest(b7e01728, f77b01b0) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7e01728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xf77b0530, CDB 0xf77b0560, AtaReq 0xb7b72000, SCmd 0x25 UniataNeedQueueing: TopLevel, qd=0 Send to device 25 TopLevel (2), srb 0xf77b0530 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77b0298 ** Ide: Command AtaReq 0xb7b72000 ** --- ** ** IdeSendCommand: SCSIOP_READ_CAPACITY PATH:LUN:TID = 0x3:0x0:0x0 ** IDE disk 0x0 - #sectors 0x3f, #heads 0xff, #cylinders 0x76c1 IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf77b0530 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b7de8728, f77b0530) AtapiStartIo: UniataRemoveRequest(b7de8728, f77b0530) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b7de8728, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf77b0168 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 40c017 CMD 0x40c017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9ae4, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xe AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 0 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x40c017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x1d0 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x1 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 1 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 1 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 2 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 2 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 3 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 3 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 4 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 4 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 5 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 5 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 6 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xe AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 0 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 1 CI 0x1 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 1 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 1 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 2 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 2 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 3 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 3 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 4 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 4 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 5 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET Save IDE retry status 5 do nothing chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 1 CI 0x1 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xc & 0x8 SRB 0xb7b18520, CDB 0xb7b18550, AtaReq 0xb7b72000, SCmd 0x28 UniataNeedQueueing: TopLevel, qd=0 Send to device 28 TopLevel (2), srb 0xb7b18520 TopLevel (3), AtaReq 0xb7b72000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0x809f9a24 ** Ide: Command AtaReq 0xb7b72000 ** --- ** IdeSendCommand: SCSIOP_READ PATH:LUN:TID = 0x3:0x0:0x0 IdeReadWrite (Orig REQ): Starting sector 0, OrigWordsRequested 0x100, DevSize 0x1 IdeReadWrite (REQ): Starting sector is 0, Number of WORDS 0x100, DevSize 0x1 IdeReadWrite: Retry after BUS_RESET 6 @0x0 (0x1) AtaReq 0xb7b72000: cmd aligned b7b72080, d=20 ahci_cmd_ptr 0xb7b72080 AtapiDmaSetup: mode 0x48, data f773a000, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b72080) AtapiVirtToPhysAddr_: b7b72080 -> 00000000:1e250080 get Phys(data[0]=f773a000) AtapiVirtToPhysAddr_: f773a000 -> 00000000:1e1c1000 set TERM ph data[0]=0:1e1c1000 (1ff) AtapiDmaSetup: OK IdeReadWrite: setup AHCI FIS AHCI setup FIS b7b72080, ch 3, dev 0 IdeReadWrite ahci io flags 5: AtapiDmaReinit: ahci, nothing to do for HDD IdeReadWrite: Lba 0x0, Count 0x1(0x0) UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b72000 AHCI AtaReq CMD 0xb7b72080 (ph 0x1e250080) prd_length 0x1, flags 0x5, base 1e250080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active IdeSendCommand: SRB_STATUS_PENDING IdeSendCommand: REQ_STATE_EXPECTING_INTR AtapiStartIo: next Srb b7b18520 AtapiStartIo: query PORT for next request AtapiResetController(0) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 0[0] CompleteType 0x1, Luns 2, chan 0xb7de8008, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x1 skip not implemented AtapiResetController(1) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 1[0] CompleteType 0x1, Luns 2, chan 0xb7de8268, sptr 0x809f9adc, flags 0x0 AHCI path imp: 0xc & 0x2 skip not implemented AtapiResetController(2) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 2[0] CompleteType 0x1, Luns 2, chan 0xb7de84c8, sptr 0x809f9adc, flags 0x100 AHCI path imp: 0xc & 0x4 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0xfd4000ff AHCI2_0x18 (0xf773f218) = 0x404017 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x50 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev process connected devices 0 - 1 Chan 0xb7de84c8 Lun 0x0 Lun ptr 0xb7de9c60 found some device IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0xc ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 ReadChannelPort4 ch2[34] = 0 WriteChannelPort4 0 => ch2[10] AHCI: is=00000000 ss=00000113 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) Chan 0xb7de84c8 Lun 0x1 Lun ptr 0xb7de9f78 device have gone AtapiResetController: deviceExtension->chan[2].DisableIntr 1 -> 1 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] imp: 0xc & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 TFD 0x100 AHCI port 2 Base: 0xf773f200 MemIo 1 Proc 0 AHCI2_0x0 (0xf773f200) = 0x1e263000 AHCI2_0x4 (0xf773f204) = 0x0 AHCI2_0x8 (0xf773f208) = 0x1e263400 AHCI2_0xc (0xf773f20c) = 0x0 AHCI2_0x10 (0xf773f210) = 0x0 AHCI2_0x14 (0xf773f214) = 0x0 AHCI2_0x18 (0xf773f218) = 0x404016 AHCI2_0x1c (0xf773f21c) = 0x0 AHCI2_0x20 (0xf773f220) = 0x100 AHCI2_0x24 (0xf773f224) = 0xeb140101 AHCI2_0x28 (0xf773f228) = 0x113 AHCI2_0x2c (0xf773f22c) = 0x300 AHCI2_0x30 (0xf773f230) = 0x0 AHCI2_0x34 (0xf773f234) = 0x0 AHCI2_0x38 (0xf773f238) = 0x0 AHCI2_0x3c (0xf773f23c) = 0x0 ReadChannelPort4 ch2[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch2[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b7deb2f8, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7b8d080) AtapiVirtToPhysAddr_: b7b8d080 -> 00000000:1e26b080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x1, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb7de9c60 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7e01d68, AtaReq 0xb7b8d000, CMD 0xb7b8d080 ph 1e26b080 AHCI setup FIS b7b8d080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7b8d000 AHCI AtaReq CMD 0xb7b8d080 (ph 0x1e26b080) prd_length 0x0, flags 0x5, base 1e26b080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x8 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xc & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x47 mode imp: 0xc & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 AtapiResetController(3) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 AtapiResetController: Reset lchannel 3[0] CompleteType 0x1, Luns 2, chan 0xb7de8728, sptr 0x809f9adc, flags 0x104 Lun 0 AtapiResetController: pending SRB 0xb7b18520, chan 0xb7de8728 senseBuffer 0xb7b73000, chan 0xb7de8728, ReqFlags 0xf AtapiResetController: report SCSI_SENSE_UNIT_ATTENTION + SCSI_ADSENSE_BUS_RESET chan 0xb7de8728 AHCI path imp: 0xc & 0x8 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x1 AHCI3_0x14 (0xf773f294) = 0xfd4000ff AHCI3_0x18 (0xf773f298) = 0x404017 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x50 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev process connected devices 0 - 1 Chan 0xb7de8728 Lun 0x0 Lun ptr 0xb7dea290 found some device IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x8 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 ReadChannelPort4 ch3[34] = 0 WriteChannelPort4 0 => ch3[10] AHCI: is=00000000 ss=00000123 serror=00000000 CI=00000000, ACT=00000000 AHCI: complete mask 0x1 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) Chan 0xb7de8728 Lun 0x1 Lun ptr 0xb7dea5a8 device have gone AtapiResetController: deviceExtension->chan[3].DisableIntr 1 -> 1 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] imp: 0xc & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x300 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 TFD 0x150 AHCI port 3 Base: 0xf773f280 MemIo 1 Proc 0 AHCI3_0x0 (0xf773f280) = 0x1e261000 AHCI3_0x4 (0xf773f284) = 0x0 AHCI3_0x8 (0xf773f288) = 0x1e261400 AHCI3_0xc (0xf773f28c) = 0x0 AHCI3_0x10 (0xf773f290) = 0x0 AHCI3_0x14 (0xf773f294) = 0x0 AHCI3_0x18 (0xf773f298) = 0x404016 AHCI3_0x1c (0xf773f29c) = 0x0 AHCI3_0x20 (0xf773f2a0) = 0x150 AHCI3_0x24 (0xf773f2a4) = 0x101 AHCI3_0x28 (0xf773f2a8) = 0x123 AHCI3_0x2c (0xf773f2ac) = 0x300 AHCI3_0x30 (0xf773f2b0) = 0x0 AHCI3_0x34 (0xf773f2b4) = 0x0 AHCI3_0x38 (0xf773f2b8) = 0x0 AHCI3_0x3c (0xf773f2bc) = 0x0 ReadChannelPort4 ch3[24] = 101 sig: 0x101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch3[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb7deb2f8, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b7deb2f8, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7b8e080) AtapiVirtToPhysAddr_: b7b8e080 -> 00000000:1e26c080 get Phys(data[0]=b7deb2f8) AtapiVirtToPhysAddr_: b7deb2f8 -> 00000000:1e4c92f8 set TERM ph data[0]=0:1e4c92f8 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x1, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=0 tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb7dea290 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 1 CI 0x1 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7e01da8, AtaReq 0xb7b8e000, CMD 0xb7b8e080 ph 1e26c080 AHCI setup FIS b7b8e080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7b8e000 AHCI AtaReq CMD 0xb7b8e080 (ph 0x1e26c080) prd_length 0x0, flags 0x5, base 1e26c080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xc & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x48 mode imp: 0xc & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiResetController(4) AtapiResetController: Reset IDE 0x1022/0x7901 @ 0x0 simplexOnly 0, VM 0 (ntoskrnl/lpc/connect.c:245) Failed to reference port '\ErrorLogPort': 0xc0000034 To