=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2021.12.12 14:24:37 =~=~=~=~=~=~=~=~=~=~=~= (boot/freeldr/freeldr/disk/partition.c:420) fixme: DiskGetPartitionEntry() unimplemented for GPT (boot/freeldr/freeldr/disk/partition.c:420) fixme: DiskGetPartitionEntry() unimplemented for GPT (boot/freeldr/freeldr/disk/partition.c:420) fixme: DiskGetPartitionEntry() unimplemented for GPT (boot/freeldr/freeldr/disk/partition.c:420) fixme: DiskGetPartitionEntry() unimplemented for GPT (boot/freeldr/freeldr/ntldr/registry.c:394) err: Did not find sub key 'BiosInfo' (full \Registry\Machine\SYSTEM\CurrentControlSet\Control\BiosInfo) (boot/freeldr/freeldr/arch/i386/pc/machpc.c:223) err: PnP-BIOS failed to enumerate device nodes (boot/freeldr/freeldr/ntldr/winldr.c:628) fixme: LoadWindowsCore: SOS - TRUE (not implemented) (ntoskrnl/kd64/kdinit.c:74) ----------------------------------------------------- (ntoskrnl/kd64/kdinit.c:75) ReactOS 0.4.15-x86-dev (Build 20211212-0.4.15-dev-3474-g067c08c) (Commit 067c08c23fe20f2dfa874a0da7a48204e7a78683) (ntoskrnl/kd64/kdinit.c:76) 1 System Processor [3246 MB Memory] (ntoskrnl/kd64/kdinit.c:80) Command Line: MININT RDPATH=LIVECD.ISO RDEXPORTASCD SOS DEBUG DEBUGPORT=COM1 (ntoskrnl/kd64/kdinit.c:81) ARC Paths: ramdisk(0) \ ramdisk(0) \reactos\ (ntoskrnl/ke/i386/cpu.c:385) Support PAE (ntoskrnl/ke/i386/cpu.c:455) Supported CPU features : KF_V86_VIS KF_RDTSC KF_CR4 KF_CMOV KF_GLOBAL_PAGE KF_LARGE_PAGE KF_MTRR KF_CMPXCHG8B KF_MMX KF_WORKING_PTE KF_PAT KF_FXSR KF_FAST_SYSCALL KF_XMMI KF_XMMI64 KF_NX_BIT (ntoskrnl/ke/i386/cpu.c:727) Prefetch Cache: 64 bytes L2 Cache: 524288 bytes L2 Cache Line: 64 bytes L2 Cache Associativity: 8 (ntoskrnl/mm/ARM3/mminit.c:1452) HAL I/O Mapping at FFFE0000 is unsafe (ntoskrnl/mm/mminit.c:134) 0x80000000 - 0xA2C00000 Boot Loaded Image (ntoskrnl/mm/mminit.c:138) 0xB0000000 - 0xB1CD5000 PFN Database (ntoskrnl/mm/mminit.c:142) 0xB1CD5000 - 0xB77BD000 ARM3 Non Paged Pool (ntoskrnl/mm/mminit.c:146) 0xB9400000 - 0xBB400000 System View Space (ntoskrnl/mm/mminit.c:150) 0xBB400000 - 0xC0000000 Session Space (ntoskrnl/mm/mminit.c:153) 0xC0000000 - 0xC03FFFFF Page Tables (ntoskrnl/mm/mminit.c:156) 0xC0300000 - 0xC0300FFF Page Directories (ntoskrnl/mm/mminit.c:159) 0xC0400000 - 0xC07FFFFF Hyperspace (ntoskrnl/mm/mminit.c:162) 0xC1000000 - 0xE0FFFFFF System Cache (ntoskrnl/mm/mminit.c:166) 0xE1000000 - 0xECC00000 ARM3 Paged Pool (ntoskrnl/mm/mminit.c:169) 0xECC00000 - 0xF7BE0000 System PTE Space (ntoskrnl/mm/mminit.c:172) 0xF7BE0000 - 0xFFBE0000 Non Paged Pool Expansion PTE Space (ntoskrnl/config/cmcheck.c:25) CmCheckRegistry(0xB77AD008, 2) is UNIMPLEMENTED! (ntoskrnl/ex/time.c:237) RtlQueryTimeZoneInformation() failed (Status 0xc0000034) (hal/halx86/legacy/bussupp.c:682) Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail! (hal/halx86/legacy/bussupp.c:711) Found parent bus (indicating PCI Bridge). PCI devices may fail! ====== PCI BUS HARDWARE DETECTION ======= 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] (rev 00) Subsystem: Unknown [1043:8747] Flags: fast devsel, latency 0 00:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) I/O Memory Management Unit [1022:1451] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (rev 00) Flags: bus master, fast devsel, latency 0 Bridge: primary bus 0, secondary bus 1, subordinate bus 1, secondary latency 0 00:01.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (rev 00) Flags: bus master, fast devsel, latency 0 Bridge: primary bus 0, secondary bus 2, subordinate bus 9, secondary latency 0 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:03.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (rev 00) Flags: bus master, fast devsel, latency 0 Bridge: primary bus 0, secondary bus 10, subordinate bus 10, secondary latency 0 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (rev 00) Flags: bus master, fast devsel, latency 0, IRQ assignment required Bridge: primary bus 0, secondary bus 11, subordinate bus 11, secondary latency 0 00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (rev 00) Flags: bus master, fast devsel, latency 0, IRQ assignment required Bridge: primary bus 0, secondary bus 12, subordinate bus 12, secondary latency 0 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 59) Subsystem: Unknown [1043:8747] Flags: 66MHz, medium devsel, latency 0 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51) Subsystem: Unknown [1043:8747] Flags: bus master, 66MHz, medium devsel, latency 0 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0 [1022:1460] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1 [1022:1461] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2 [1022:1462] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3 [1022:1463] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4 [1022:1464] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5 [1022:1465] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6 [1022:1466] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7 [1022:1467] (rev 00) Subsystem: Unknown [0000:0000] Flags: fast devsel, latency 0 01:00.0 Non-Volatile memory controller [0108]: Shenzhen Longsys Electronics Co., Ltd. Unknown device [1d97:1d97] (rev 01) Subsystem: Unknown [1d97:1d97] Flags: bus master, fast devsel, latency 0, IRQ 11 Memory at fcd20000 (64-bit, non-prefetchable) [size=128K] Device is using IRQ 11! ISA Cards using that IRQ may fail! 02:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse Switch Upstream [1022:57ad] (rev 00) Flags: bus master, fast devsel, latency 0, IRQ 10 Bridge: primary bus 2, secondary bus 3, subordinate bus 9, secondary latency 0 03:01.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (rev 00) Flags: bus master, fast devsel, latency 0 Bridge: primary bus 3, secondary bus 4, subordinate bus 4, secondary latency 0 03:02.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (rev 00) Flags: bus master, fast devsel, latency 0 Bridge: primary bus 3, secondary bus 5, subordinate bus 5, secondary latency 0 03:05.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (rev 00) Flags: bus master, fast devsel, latency 0 Bridge: primary bus 3, secondary bus 6, subordinate bus 6, secondary latency 0 03:08.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4] (rev 00) Flags: bus master, fast devsel, latency 0, IRQ 10 Bridge: primary bus 3, secondary bus 7, subordinate bus 7, secondary latency 0 03:09.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4] (rev 00) Flags: bus master, fast devsel, latency 0, IRQ 15 Bridge: primary bus 3, secondary bus 8, subordinate bus 8, secondary latency 0 03:0a.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4] (rev 00) Flags: bus master, fast devsel, latency 0, IRQ 05 Bridge: primary bus 3, secondary bus 9, subordinate bus 9, secondary latency 0 04:00.0 Non-Volatile memory controller [0108]: Silicon Motion, Inc. SM2262/SM2262EN SSD Controller [126f:2262] (rev 03) Subsystem: Unknown [126f:2262] Flags: bus master, fast devsel, latency 0, IRQ 15 Memory at fc800000 (64-bit, non-prefetchable) [size=8M] Device is using IRQ 15! ISA Cards using that IRQ may fail! 05:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM2142 USB 3.1 Host Controller [1b21:2142] (rev 00) Subsystem: Unknown [1b21:2142] Flags: bus master, fast devsel, latency 0, IRQ 05 Memory at fc700000 (64-bit, non-prefetchable) [size=1M] Device is using IRQ 5! ISA Cards using that IRQ may fail! 06:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 26) Subsystem: Unknown [1043:87c3] Flags: bus master, fast devsel, latency 0, IRQ 15 I/O ports at f000 [size=4K] Memory at fc604000 (64-bit, non-prefetchable) [size=16K] Memory at fc600000 (64-bit, non-prefetchable) [size=2M] Device is using IRQ 15! ISA Cards using that IRQ may fail! 07:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 07:00.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at fc300000 (64-bit, non-prefetchable) [size=1M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 07:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c] (rev 00) Subsystem: Unknown [1022:148c] Flags: bus master, fast devsel, latency 0, IRQ 05 Memory at fc200000 (64-bit, non-prefetchable) [size=2M] Device is using IRQ 5! ISA Cards using that IRQ may fail! 08:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) Subsystem: Unknown [1022:7901] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at fc500000 (32-bit, non-prefetchable) [size=1M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 09:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) Subsystem: Unknown [1022:7901] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at fc400000 (32-bit, non-prefetchable) [size=4M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 0a:00.0 VGA compatible controller [0300]: NVIDIA Corporation GP106 [GeForce GTX 1060 6GB] [10de:1c03] (rev a1) Subsystem: Unknown [1043:85ab] Flags: bus master, fast devsel, latency 0, IRQ 05 Memory at fb000000 (32-bit, non-prefetchable) [size=16M] Memory at d0000000 (64-bit, prefetchable) [size=256M] Memory at e0000000 (64-bit, prefetchable) [size=512M] I/O ports at e000 [size=8K] Device is using IRQ 5! ISA Cards using that IRQ may fail! 0a:00.1 Audio device [0403]: NVIDIA Corporation GP106 High Definition Audio Controller [10de:10f1] (rev a1) Subsystem: Unknown [1043:85ab] Flags: bus master, fast devsel, latency 0, IRQ 14 Memory at fc080000 (32-bit, non-prefetchable) [size=512K] Device is using IRQ 14! ISA Cards using that IRQ may fail! 0b:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 0b:00.2 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at fca00000 (32-bit, non-prefetchable) [size=2M] Memory at fcb00000 (32-bit, non-prefetchable) [size=1M] Device is using IRQ 10! ISA Cards using that IRQ may fail! 0b:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:145f] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 15 Memory at fc900000 (64-bit, non-prefetchable) [size=1M] Device is using IRQ 15! ISA Cards using that IRQ may fail! 0c:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] (rev 00) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0 0c:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) Subsystem: Unknown [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 11 Memory at fcc08000 (32-bit, non-prefetchable) [size=32K] Device is using IRQ 11! ISA Cards using that IRQ may fail! 0c:00.3 Audio device [0403]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) HD Audio Controller [1022:1457] (rev 00) Subsystem: Unknown [1043:8797] Flags: bus master, fast devsel, latency 0, IRQ 10 Memory at fcc00000 (32-bit, non-prefetchable) [size=4M] Device is using IRQ 10! ISA Cards using that IRQ may fail! ====== PCI BUS DETECTION COMPLETE ======= PC Compatible Eisa/Isa HAL Detected WARNING: ArbInitializeArbiterInstance at sdk/lib/drivers/arbiter/arbiter.c:38 is UNIMPLEMENTED! WARNING: ArbInitializeArbiterInstance at sdk/lib/drivers/arbiter/arbiter.c:38 is UNIMPLEMENTED! WARNING: ArbInitializeArbiterInstance at sdk/lib/drivers/arbiter/arbiter.c:38 is UNIMPLEMENTED! WARNING: ArbInitializeArbiterInstance at sdk/lib/drivers/arbiter/arbiter.c:38 is UNIMPLEMENTED! WARNING: ArbInitializeArbiterInstance at sdk/lib/drivers/arbiter/arbiter.c:38 is UNIMPLEMENTED! (ntoskrnl/io/iomgr/driver.c:636) '\Driver\sacdrv' initialization failed, status (0xc0000037) (ntoskrnl/io/iomgr/driver.c:85) Deleting driver object '\Driver\sacdrv' (ntoskrnl/mm/ARM3/sysldr.c:955) Leaking driver: sacdrv.sys (ntoskrnl/io/iomgr/driver.c:901) Driver 'SACDRV.SYS' load failed, status (c0000365) (ntoskrnl/io/pnpmgr/devaction.c:652) Failed to open class key "{4D36E968-E325-11CE-BFC1-08002BE10318}" (status c0000034) (hal/halx86/legacy/bus/bushndlr.c:126) STUB Adjustment ATAPI IDE MiniPort Driver (UniATA) v 0.47a HwInitializationDataSize = 50 UniATA: parse ArgumentString (drivers/storage/port/scsiport/scsiport.c:984) Created device: \Device\ScsiPort0 (B7123038) (drivers/storage/port/scsiport/scsiport.c:2497) ZwOpenKey() failed with Status=0xC0000034 Parameter PrintLogo Parameter PrintLogo = 0x0 Parameter IgnoreIsaCompatiblePci Parameter IgnoreIsaCompatiblePci = 0x0 Parameter IgnoreNativePci Parameter IgnoreNativePci = 0x0 UniATA Init: OS should be ReactOS UniATA Init: OS ver 4.1 (1), 1 CPU(s) Performance calibration: dt=14995, counter=3929921 InitBadBlocks general InitBadBlocks returned: 0xc0000034 Parameter SkipRaids Parameter SkipRaids = 0x1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 Parameter LogToDisplay Parameter LogToDisplay = 0x0 set NeedPhysicalAddresses = TRUE set AtapiAdapterControl() ptr UniATA init... (0) Parameter VirtualMachineType Parameter VirtualMachineType = 0x0 Parameter VirtualBox Parameter VirtualBox = 0x0 ATAPI IDE enum supported PCI BusMaster Devices UniataEnumBusMasterController__: maxPciBus=16 pass 0 DevId = 14501022 Class = 0006/0000, SubVen/Sys 1043/8747 DevId = 14511022 Class = 0008/0006, SubVen/Sys 1043/8747 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14531022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14531022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14531022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14541022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 14521022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14541022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 790B1022 Class = 000C/0005, SubVen/Sys 1043/8747 DevId = 790E1022 Class = 0006/0001, SubVen/Sys 1043/8747 DevId = 14601022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14611022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14621022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14631022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14641022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14651022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14661022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 14671022 Class = 0006/0000, SubVen/Sys 0000/0000 DevId = 1D971D97 Class = 0001/0008, SubVen/Sys 1d97/1d97 -- BusID: 0x1:0x0:0x0 Storage Class DevId = 1D971D97 Class = 0001/0008, ProgIf 02 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Subclass not supported Subclass not supported DevId = 57AD1022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A31022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A31022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A31022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A41022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A41022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 57A41022 Class = 0006/0004, SubVen/Sys 0000/0000 DevId = 2262126F Class = 0001/0008, SubVen/Sys 126f/2262 -- BusID: 0x4:0x0:0x0 Storage Class DevId = 2262126F Class = 0001/0008, ProgIf 02 (!) InterruptPin = 0x1 (!) InterruptLine = 0xf Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Subclass not supported Subclass not supported DevId = 21421B21 Class = 000C/0003, SubVen/Sys 1b21/2142 DevId = 816810EC Class = 0002/0000, SubVen/Sys 1043/87c3 DevId = 14851022 Class = 0013/0000, SubVen/Sys 1043/8747 DevId = 149C1022 Class = 000C/0003, SubVen/Sys 1043/8747 DevId = 149C1022 Class = 000C/0003, SubVen/Sys 1022/148c DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x8:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 0 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xfc500000 count: BMListLen++ DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x9:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 0 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xfc400000 count: BMListLen++ DevId = 1C0310DE Class = 0003/0000, SubVen/Sys 1043/85ab DevId = 10F110DE Class = 0004/0003, SubVen/Sys 1043/85ab DevId = 145A1022 Class = 0013/0000, SubVen/Sys 1043/8747 DevId = 14561022 Class = 0010/0080, SubVen/Sys 1043/8747 DevId = 145F1022 Class = 000C/0003, SubVen/Sys 1043/8747 DevId = 14551022 Class = 0013/0000, SubVen/Sys 1043/8747 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1043/8747 -- BusID: 0xc:0x0:0x2 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 0 InterruptPin = 0x2 InterruptLine = 0xb Range 5 = 0xfcc08000 count: BMListLen++ DevId = 14571022 Class = 0004/0003, SubVen/Sys 1043/8797 pass 1 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x8:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 1 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xfc500000 found suitable device DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x9:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 1 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xfc400000 found suitable device DevId = 79011022 Class = 0001/0006, SubVen/Sys 1043/8747 -- BusID: 0xc:0x0:0x2 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 1 InterruptPin = 0x2 InterruptLine = 0xb Range 5 = 0xfcc08000 found suitable device pass 2 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x8:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 2 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xfc500000 found suitable device Add to BMList, AltInit 0 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1022/7901 -- BusID: 0x9:0x0:0x0 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 2 InterruptPin = 0x1 InterruptLine = 0xa Range 5 = 0xfc400000 found suitable device Add to BMList, AltInit 0 DevId = 79011022 Class = 0001/0006, SubVen/Sys 1043/8747 -- BusID: 0xc:0x0:0x2 Storage Class DevId = 79011022 Class = 0001/0006, ProgIf 01 Parameter Include Parameter Include = 0x0 No force include, check exclude Parameter Exclude Parameter Exclude = 0x0 unknown Default device found, pass 2 InterruptPin = 0x2 InterruptLine = 0xb Range 5 = 0xfcc08000 found suitable device Add to BMList, AltInit 0 BMListLen=3 Parameter WaitBusyCount Parameter WaitBusyCount = 0xc8 Parameter WaitBusyDelay Parameter WaitBusyDelay = 0xa Parameter WaitDrqDelay Parameter WaitDrqDelay = 0xa Parameter WaitBusyLongCount Parameter WaitBusyLongCount = 0x7d0 Parameter WaitBusyLongDelay Parameter WaitBusyLongDelay = 0xfa Parameter AtapiSendDisableIntr Parameter AtapiSendDisableIntr = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiNoDma Parameter AtapiNoDma = 0x0 Parameter MaxIsrWait Parameter MaxIsrWait = 0x28 Parameter DriveSelectNanoDelay Parameter DriveSelectNanoDelay = 0x0 ATAPI IDE: Look for legacy ISA-bridged PCI IDE controller (onboard) ATAPI IDE: BMListLen 3 !BMList[i].MasterDev ATAPI IDE: Look for PCI IDE controller ATAPI IDE: i 0, BMListLen 3 Try init 1022 7901 (drivers/storage/port/scsiport/scsiport.c:984) Created device: \Device\ScsiPort0 (B7123038) (hal/halx86/legacy/bussupp.c:1284) Slot assignment for 5 on bus 8 (hal/halx86/legacy/bus/pcibus.c:728) WARNING: PCI Slot Resource Assignment is FOOBAR UniataFindBusMasterController: Context=0, BMListLen=3 ConfigInfo->Length 8c bm_offset 0, channel 0 AdapterInterfaceType=0x5 IoBusNumber=0x8 slotNumber=0x0 busDataRead DevId = 79011022 Class = 0001/0006 Storage Class unknown UniataChipDetect: HwFlags: 0x0 Parameter ForceSimplex Parameter ForceSimplex = 0x0 i: 0xf VendorID/DeviceID/Rev 0x1022/0x7901/0x51 i: 0xffffffff AHCI candidate UniataAhciDetect: Parameter IgnoreAhci Parameter IgnoreAhci = 0x0 AtapiGetIoRange: AtapiGetIoRange: rid 0x5, start 0x0, offs 0x0, len 0x10, mem 0x0 AtapiGetIoRange: adjust mem 0 -> 1 AtapiGetIoRange: 0xf738d000 MemIo AHCI Base: 0xf738d000 MemIo 1 Proc 0 AHCI_0x0 (0xf738d000) = 0xf737ff03 AHCI_0x4 (0xf738d004) = 0x80000000 AHCI_0x8 (0xf738d008) = 0x0 AHCI_0xc (0xf738d00c) = 0xf AHCI_0x10 (0xf738d010) = 0x10301 check AHCI mode, GHC 0x80000000 AHCI CAP 0xf737ff03, CAP2 0x0, ver 0x10301 64bit NCQ SNTF AHCI PI 0xf Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter PortMask Parameter PortMask = 0xf Force PortMask 0xf CommandSlots 31 Detected Channels 4 / 4 Adjusted Channels 4 AHCI version 1.31 controller with 4 ports (mask 0xf) detected AHCI SATA Gen 3 PM supported Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 AHCI detect status 1 unknown AHCI dev, addr 0xf738d000 unknown dev, BM addr 0x0 MaxTransferMode 0x49 UniataChipDetectChannels: Parameter IgnoreAhciPM Parameter IgnoreAhciPM = 0x1 SATA/AHCI w/o PM, max luns 1 or 2 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter Exclude Parameter Exclude = 0x0 PortMask 0xf Parameter PortMask Parameter PortMask = 0xf Force PortMask 0xf mask -> 4 chans Parameter NumberChannels Parameter NumberChannels = 0x4 reg -> 4 chans Final PortMask 0xf allocate 2 Luns for 4 channels ForceSimplex = 0 HwFlags = 12000000 (0)HwFlags = 12000000 (1)HwFlags = 12000000 (2)found suitable device HwFlags = 12000000 (3) AHCI registers layout AtapiReadChipConfig: devExt 0xb71232b0 AtapiReadChipConfig: dev 0x0, ph chan -1 Parameter ForceSimplex Parameter ForceSimplex = 0x0 MaxTransferMode (base): 0x49 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter Force80pin Parameter Force80pin = 0x0 Parameter AtapiDmaZeroTransfer Parameter AtapiDmaZeroTransfer = 0x0 Parameter AtapiDmaControlCmd Parameter AtapiDmaControlCmd = 0x0 Parameter AtapiDmaRawRead Parameter AtapiDmaRawRead = 0x1 Parameter AtapiDmaReadWrite Parameter AtapiDmaReadWrite = 0x1 AtapiChipInit: dev 0x0, ph chan -2, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf738d000 MemIo 1 Proc 0 AHCI_0x0 (0xf738d000) = 0xf737ff03 AHCI_0x4 (0xf738d004) = 0x80000000 AHCI_0x8 (0xf738d008) = 0x0 AHCI_0xc (0xf738d00c) = 0xf AHCI_0x10 (0xf738d010) = 0x10301 get GHC disable intr, GHC 0x80000000 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff03 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0xf AHCI PI mask 0xf masked AHCI PI 0xf SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb711c008 Lun 0x0 Lun ptr 0xb711d000 Lun 0x1 Lun ptr 0xb711d318 AtaReq 0xb711f000: cmd aligned b711f080, d=20 ahci_cmd_ptr 0xb711f080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b711a000 AtapiDmaAlloc: CLP BASE 1k-aligned b711a000 AtapiVirtToPhysAddr_: b711a000 -> 00000000:27cca000 AtapiDmaAlloc: CLP Phys BASE 27cca000 imp: 0xf & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 27cca000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 27cca400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 400040 WriteChannelPort4 400040 => ch0[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch0[18] ReadChannelPort4 ch0[18] = 40e017 AHCI port 0 Base: 0xf738d100 MemIo 1 Proc 0 AHCI0_0x0 (0xf738d100) = 0x27cca000 AHCI0_0x4 (0xf738d104) = 0x0 AHCI0_0x8 (0xf738d108) = 0x27cca400 AHCI0_0xc (0xf738d10c) = 0x0 AHCI0_0x10 (0xf738d110) = 0x400040 AHCI0_0x14 (0xf738d114) = 0x0 AHCI0_0x18 (0xf738d118) = 0x40e017 AHCI0_0x1c (0xf738d11c) = 0x0 AHCI0_0x20 (0xf738d120) = 0x150 AHCI0_0x24 (0xf738d124) = 0x101 AHCI0_0x28 (0xf738d128) = 0x133 AHCI0_0x2c (0xf738d12c) = 0x0 AHCI0_0x30 (0xf738d130) = 0x4050000 AHCI0_0x34 (0xf738d134) = 0x0 AHCI0_0x38 (0xf738d138) = 0x0 AHCI0_0x3c (0xf738d13c) = 0x0 chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb711c268 Lun 0x0 Lun ptr 0xb711d630 Lun 0x1 Lun ptr 0xb711d948 AtaReq 0xb7120000: cmd aligned b7120080, d=20 ahci_cmd_ptr 0xb7120080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7118000 AtapiDmaAlloc: CLP BASE 1k-aligned b7118000 AtapiVirtToPhysAddr_: b7118000 -> 00000000:27cc8000 AtapiDmaAlloc: CLP Phys BASE 27cc8000 imp: 0xf & 0x2 UniataAhciResume: lChan 1 WriteChannelPort4 0 => ch1[14] AHCI CLB setup WriteChannelPort4 27cc8000 => ch1[0] WriteChannelPort4 0 => ch1[4] AHCI RCV FIS setup WriteChannelPort4 27cc8400 => ch1[8] WriteChannelPort4 0 => ch1[c] WriteChannelPort4 10000006 => ch1[18] ReadChannelPort4 ch1[18] = 402006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 400040 WriteChannelPort4 400040 => ch1[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch1[18] ReadChannelPort4 ch1[18] = 40e017 AHCI port 1 Base: 0xf738d180 MemIo 1 Proc 0 AHCI1_0x0 (0xf738d180) = 0x27cc8000 AHCI1_0x4 (0xf738d184) = 0x0 AHCI1_0x8 (0xf738d188) = 0x27cc8400 AHCI1_0xc (0xf738d18c) = 0x0 AHCI1_0x10 (0xf738d190) = 0x400040 AHCI1_0x14 (0xf738d194) = 0x0 AHCI1_0x18 (0xf738d198) = 0x40e017 AHCI1_0x1c (0xf738d19c) = 0x0 AHCI1_0x20 (0xf738d1a0) = 0x150 AHCI1_0x24 (0xf738d1a4) = 0x101 AHCI1_0x28 (0xf738d1a8) = 0x123 AHCI1_0x2c (0xf738d1ac) = 0x0 AHCI1_0x30 (0xf738d1b0) = 0x4050000 AHCI1_0x34 (0xf738d1b4) = 0x0 AHCI1_0x38 (0xf738d1b8) = 0x0 AHCI1_0x3c (0xf738d1bc) = 0x0 chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb711c4c8 Lun 0x0 Lun ptr 0xb711dc60 Lun 0x1 Lun ptr 0xb711df78 AtaReq 0xb7121000: cmd aligned b7121080, d=20 ahci_cmd_ptr 0xb7121080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7116000 AtapiDmaAlloc: CLP BASE 1k-aligned b7116000 AtapiVirtToPhysAddr_: b7116000 -> 00000000:27cc6000 AtapiDmaAlloc: CLP Phys BASE 27cc6000 imp: 0xf & 0x4 UniataAhciResume: lChan 2 WriteChannelPort4 0 => ch2[14] AHCI CLB setup WriteChannelPort4 27cc6000 => ch2[0] WriteChannelPort4 0 => ch2[4] AHCI RCV FIS setup WriteChannelPort4 27cc6400 => ch2[8] WriteChannelPort4 0 => ch2[c] WriteChannelPort4 10000006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 400040 WriteChannelPort4 400040 => ch2[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 AHCI port 2 Base: 0xf738d200 MemIo 1 Proc 0 AHCI2_0x0 (0xf738d200) = 0x27cc6000 AHCI2_0x4 (0xf738d204) = 0x0 AHCI2_0x8 (0xf738d208) = 0x27cc6400 AHCI2_0xc (0xf738d20c) = 0x0 AHCI2_0x10 (0xf738d210) = 0x400040 AHCI2_0x14 (0xf738d214) = 0x0 AHCI2_0x18 (0xf738d218) = 0x40c017 AHCI2_0x1c (0xf738d21c) = 0x0 AHCI2_0x20 (0xf738d220) = 0x150 AHCI2_0x24 (0xf738d224) = 0x101 AHCI2_0x28 (0xf738d228) = 0x123 AHCI2_0x2c (0xf738d22c) = 0x0 AHCI2_0x30 (0xf738d230) = 0x4050000 AHCI2_0x34 (0xf738d234) = 0x0 AHCI2_0x38 (0xf738d238) = 0x0 AHCI2_0x3c (0xf738d23c) = 0x0 chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb711c728 Lun 0x0 Lun ptr 0xb711e290 Lun 0x1 Lun ptr 0xb711e5a8 AtaReq 0xb7122000: cmd aligned b7122080, d=20 ahci_cmd_ptr 0xb7122080 AtapiDmaAlloc: AHCI AtapiDmaAlloc: CLP BASE b7114000 AtapiDmaAlloc: CLP BASE 1k-aligned b7114000 AtapiVirtToPhysAddr_: b7114000 -> 00000000:27cc4000 AtapiDmaAlloc: CLP Phys BASE 27cc4000 imp: 0xf & 0x8 UniataAhciResume: lChan 3 WriteChannelPort4 0 => ch3[14] AHCI CLB setup WriteChannelPort4 27cc4000 => ch3[0] WriteChannelPort4 0 => ch3[4] AHCI RCV FIS setup WriteChannelPort4 27cc4400 => ch3[8] WriteChannelPort4 0 => ch3[c] WriteChannelPort4 10000006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 400040 WriteChannelPort4 400040 => ch3[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 AHCI port 3 Base: 0xf738d280 MemIo 1 Proc 0 AHCI3_0x0 (0xf738d280) = 0x27cc4000 AHCI3_0x4 (0xf738d284) = 0x0 AHCI3_0x8 (0xf738d288) = 0x27cc4400 AHCI3_0xc (0xf738d28c) = 0x0 AHCI3_0x10 (0xf738d290) = 0x400040 AHCI3_0x14 (0xf738d294) = 0x0 AHCI3_0x18 (0xf738d298) = 0x40c017 AHCI3_0x1c (0xf738d29c) = 0x0 AHCI3_0x20 (0xf738d2a0) = 0x100 AHCI3_0x24 (0xf738d2a4) = 0xeb140101 AHCI3_0x28 (0xf738d2a8) = 0x113 AHCI3_0x2c (0xf738d2ac) = 0x0 AHCI3_0x30 (0xf738d2b0) = 0x4050000 AHCI3_0x34 (0xf738d2b4) = 0x0 AHCI3_0x38 (0xf738d2b8) = 0x0 AHCI3_0x3c (0xf738d2bc) = 0x0 simplexOnly = 0 (2)!MasterDev update ConfigInfo->nt4 using AtaReq sz 1000 update ConfigInfo->w2k: 64bit 1 chan[0] InterruptMode: 0, Level 10, Level2 0, Vector 10, Vector2 0 Reconstruct ConfigInfo set Dma32BitAddresses BMList[i].channel 0x0, NumberChannels 0x4, channel 0x0 de 0xb71232b0, Channel 0x0 chan = 0xb711c008 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb711c008 Lun 0x0 Lun ptr 0xb711d000 Lun 0x1 Lun ptr 0xb711d318 AtaReq 0xb711f000: cmd aligned b711f080, d=20 ahci_cmd_ptr 0xb711f080 AtapiReadChipConfig: devExt 0xb71232b0 AtapiReadChipConfig: dev 0x0, ph chan 0 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf738d120), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf738d128), Mem: AtapiDmaAlloc: AHCI already initialized b711a000 de 0xb71232b0, Channel 0x1 chan = 0xb711c268 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb711c268 Lun 0x0 Lun ptr 0xb711d630 Lun 0x1 Lun ptr 0xb711d948 AtaReq 0xb7120000: cmd aligned b7120080, d=20 ahci_cmd_ptr 0xb7120080 AtapiReadChipConfig: devExt 0xb71232b0 AtapiReadChipConfig: dev 0x0, ph chan 1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf738d1a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf738d1a8), Mem: AtapiDmaAlloc: AHCI already initialized b7118000 de 0xb71232b0, Channel 0x2 chan = 0xb711c4c8 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb711c4c8 Lun 0x0 Lun ptr 0xb711dc60 Lun 0x1 Lun ptr 0xb711df78 AtaReq 0xb7121000: cmd aligned b7121080, d=20 ahci_cmd_ptr 0xb7121080 AtapiReadChipConfig: devExt 0xb71232b0 AtapiReadChipConfig: dev 0x0, ph chan 2 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf738d220), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf738d228), Mem: AtapiDmaAlloc: AHCI already initialized b7116000 de 0xb71232b0, Channel 0x3 chan = 0xb711c728 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb711c728 Lun 0x0 Lun ptr 0xb711e290 Lun 0x1 Lun ptr 0xb711e5a8 AtaReq 0xb7122000: cmd aligned b7122080, d=20 ahci_cmd_ptr 0xb7122080 AtapiReadChipConfig: devExt 0xb71232b0 AtapiReadChipConfig: dev 0x0, ph chan 3 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 MaxTransferMode (overriden): 0x49 Parameter ReorderEnable Parameter ReorderEnable = 0x1 Parameter Force80pin Parameter Force80pin = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 Parameter ReadCacheEnable Parameter ReadCacheEnable = 0x1 Parameter WriteCacheEnable Parameter WriteCacheEnable = 0x1 Parameter MaxTransferMode Parameter MaxTransferMode = 0x49 Parameter PreferedTransferMode Parameter PreferedTransferMode = 0xffffffff Parameter AdvancedPowerMode Parameter AdvancedPowerMode = 0x80 Parameter AcousticMgmt Parameter AcousticMgmt = 0x80 Parameter StandbyTimer Parameter StandbyTimer = 0x0 Parameter ReadOnly Parameter ReadOnly = 0x0 Parameter GeomType Parameter GeomType = 0xffffffff Parameter Hidden Parameter Hidden = 0x0 Parameter Exclude Parameter Exclude = 0x0 No more setup for AHCI channel IO_0x0 (0x0), IO: IO_0x10 (0xf738d2a0), Mem: IO_0x12 (0x0), IO: IO_0x17 (0xf738d2a8), Mem: AtapiDmaAlloc: AHCI already initialized b7114000 exit: init spinlock MasterDev=0x0, NumberChannels=0x4, Isr2DevObj=0x0 Init ISR: Multichannel native mode, go... Create DO DO name: len(38, 38), \Device\uniata0_2ch HalGetInterruptVector OrigAdapterInterfaceType=5 SystemIoBusNumber=8 BusInterruptLevel=10 BusInterruptVector=10 isr2_de 0xb711ce00 isr2_vector 0x3a isr2_irql 0x11 isr2_affinity 0x1 IoConnectInterrupt MasterDev=0x0, NumberChannels=0x4, Isr2DevObj=0xb711cd48 final chan[4] InterruptMode: 0, Level 10, Level2 0, Vector 10, Vector2 0 return SP_RETURN_FOUND AtapiHwInitialize: (base) AtapiChipInit: dev 0xffffffff, ph chan -1, c -1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 UniataAhciInit: AHCI Base: 0xf738d000 MemIo 1 Proc 0 AHCI_0x0 (0xf738d000) = 0xf737ff03 AHCI_0x4 (0xf738d004) = 0x80000002 AHCI_0x8 (0xf738d008) = 0x0 AHCI_0xc (0xf738d00c) = 0xf AHCI_0x10 (0xf738d010) = 0x10301 get GHC disable intr, GHC 0x80000002 reset AHCI controller, GHC 0x80000000 AHCI GHC 0x80000000 AHCI GHC 0x80000000 AHCI CAP 0xf737ff03 AHCI 64bit AHCI 31 CMD slots AHCI multi-block PIO AHCI legasy SATA AHCI PI 0xf AHCI PI mask 0xf masked AHCI PI 0xf SATA Gen 3 chan 0, offs 0x100 AtapiSetupLunPtrs for channel 0 of 4, 2 luns Chan 0xb711c008 Lun 0x0 Lun ptr 0xb711d000 Lun 0x1 Lun ptr 0xb711d318 AtaReq 0xb711f000: cmd aligned b711f080, d=20 ahci_cmd_ptr 0xb711f080 AtapiDmaAlloc: AHCI already initialized b711a000 imp: 0xf & 0x1 UniataAhciResume: lChan 0 WriteChannelPort4 0 => ch0[14] AHCI CLB setup WriteChannelPort4 27cca000 => ch0[0] WriteChannelPort4 0 => ch0[4] AHCI RCV FIS setup WriteChannelPort4 27cca400 => ch0[8] WriteChannelPort4 0 => ch0[c] WriteChannelPort4 10000006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 400040 WriteChannelPort4 400040 => ch0[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch0[18] ReadChannelPort4 ch0[18] = 40e017 AHCI port 0 Base: 0xf738d100 MemIo 1 Proc 0 AHCI0_0x0 (0xf738d100) = 0x27cca000 AHCI0_0x4 (0xf738d104) = 0x0 AHCI0_0x8 (0xf738d108) = 0x27cca400 AHCI0_0xc (0xf738d10c) = 0x0 AHCI0_0x10 (0xf738d110) = 0x400040 AHCI0_0x14 (0xf738d114) = 0x0 AHCI0_0x18 (0xf738d118) = 0x40e017 AHCI0_0x1c (0xf738d11c) = 0x0 AHCI0_0x20 (0xf738d120) = 0x150 AHCI0_0x24 (0xf738d124) = 0x101 AHCI0_0x28 (0xf738d128) = 0x133 AHCI0_0x2c (0xf738d12c) = 0x0 AHCI0_0x30 (0xf738d130) = 0x4050000 AHCI0_0x34 (0xf738d134) = 0x0 AHCI0_0x38 (0xf738d138) = 0x0 AHCI0_0x3c (0xf738d13c) = 0x0 chan 1, offs 0x180 AtapiSetupLunPtrs for channel 1 of 4, 2 luns Chan 0xb711c268 Lun 0x0 Lun ptr 0xb711d630 Lun 0x1 Lun ptr 0xb711d948 AtaReq 0xb7120000: cmd aligned b7120080, d=20 ahci_cmd_ptr 0xb7120080 AtapiDmaAlloc: AHCI already initialized b7118000 imp: 0xf & 0x2 UniataAhciResume: lChan 1 WriteChannelPort4 0 => ch1[14] AHCI CLB setup WriteChannelPort4 27cc8000 => ch1[0] WriteChannelPort4 0 => ch1[4] AHCI RCV FIS setup WriteChannelPort4 27cc8400 => ch1[8] WriteChannelPort4 0 => ch1[c] WriteChannelPort4 10000006 => ch1[18] ReadChannelPort4 ch1[18] = 402006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 400040 WriteChannelPort4 400040 => ch1[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch1[18] ReadChannelPort4 ch1[18] = 40e017 AHCI port 1 Base: 0xf738d180 MemIo 1 Proc 0 AHCI1_0x0 (0xf738d180) = 0x27cc8000 AHCI1_0x4 (0xf738d184) = 0x0 AHCI1_0x8 (0xf738d188) = 0x27cc8400 AHCI1_0xc (0xf738d18c) = 0x0 AHCI1_0x10 (0xf738d190) = 0x400040 AHCI1_0x14 (0xf738d194) = 0x0 AHCI1_0x18 (0xf738d198) = 0x40e017 AHCI1_0x1c (0xf738d19c) = 0x0 AHCI1_0x20 (0xf738d1a0) = 0x150 AHCI1_0x24 (0xf738d1a4) = 0x101 AHCI1_0x28 (0xf738d1a8) = 0x123 AHCI1_0x2c (0xf738d1ac) = 0x0 AHCI1_0x30 (0xf738d1b0) = 0x4050000 AHCI1_0x34 (0xf738d1b4) = 0x0 AHCI1_0x38 (0xf738d1b8) = 0x0 AHCI1_0x3c (0xf738d1bc) = 0x0 chan 2, offs 0x200 AtapiSetupLunPtrs for channel 2 of 4, 2 luns Chan 0xb711c4c8 Lun 0x0 Lun ptr 0xb711dc60 Lun 0x1 Lun ptr 0xb711df78 AtaReq 0xb7121000: cmd aligned b7121080, d=20 ahci_cmd_ptr 0xb7121080 AtapiDmaAlloc: AHCI already initialized b7116000 imp: 0xf & 0x4 UniataAhciResume: lChan 2 WriteChannelPort4 0 => ch2[14] AHCI CLB setup WriteChannelPort4 27cc6000 => ch2[0] WriteChannelPort4 0 => ch2[4] AHCI RCV FIS setup WriteChannelPort4 27cc6400 => ch2[8] WriteChannelPort4 0 => ch2[c] WriteChannelPort4 10000006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 400040 WriteChannelPort4 400040 => ch2[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 AHCI port 2 Base: 0xf738d200 MemIo 1 Proc 0 AHCI2_0x0 (0xf738d200) = 0x27cc6000 AHCI2_0x4 (0xf738d204) = 0x0 AHCI2_0x8 (0xf738d208) = 0x27cc6400 AHCI2_0xc (0xf738d20c) = 0x0 AHCI2_0x10 (0xf738d210) = 0x400040 AHCI2_0x14 (0xf738d214) = 0x0 AHCI2_0x18 (0xf738d218) = 0x40c017 AHCI2_0x1c (0xf738d21c) = 0x0 AHCI2_0x20 (0xf738d220) = 0x150 AHCI2_0x24 (0xf738d224) = 0x101 AHCI2_0x28 (0xf738d228) = 0x123 AHCI2_0x2c (0xf738d22c) = 0x0 AHCI2_0x30 (0xf738d230) = 0x4050000 AHCI2_0x34 (0xf738d234) = 0x0 AHCI2_0x38 (0xf738d238) = 0x0 AHCI2_0x3c (0xf738d23c) = 0x0 chan 3, offs 0x280 AtapiSetupLunPtrs for channel 3 of 4, 2 luns Chan 0xb711c728 Lun 0x0 Lun ptr 0xb711e290 Lun 0x1 Lun ptr 0xb711e5a8 AtaReq 0xb7122000: cmd aligned b7122080, d=20 ahci_cmd_ptr 0xb7122080 AtapiDmaAlloc: AHCI already initialized b7114000 imp: 0xf & 0x8 UniataAhciResume: lChan 3 WriteChannelPort4 0 => ch3[14] AHCI CLB setup WriteChannelPort4 27cc4000 => ch3[0] WriteChannelPort4 0 => ch3[4] AHCI RCV FIS setup WriteChannelPort4 27cc4400 => ch3[8] WriteChannelPort4 0 => ch3[c] WriteChannelPort4 10000006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 400040 WriteChannelPort4 400040 => ch3[10] SError 0x4050000, IS 0x400040 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 AHCI port 3 Base: 0xf738d280 MemIo 1 Proc 0 AHCI3_0x0 (0xf738d280) = 0x27cc4000 AHCI3_0x4 (0xf738d284) = 0x0 AHCI3_0x8 (0xf738d288) = 0x27cc4400 AHCI3_0xc (0xf738d28c) = 0x0 AHCI3_0x10 (0xf738d290) = 0x400040 AHCI3_0x14 (0xf738d294) = 0x0 AHCI3_0x18 (0xf738d298) = 0x40c017 AHCI3_0x1c (0xf738d29c) = 0x0 AHCI3_0x20 (0xf738d2a0) = 0x100 AHCI3_0x24 (0xf738d2a4) = 0xeb140101 AHCI3_0x28 (0xf738d2a8) = 0x113 AHCI3_0x2c (0xf738d2ac) = 0x0 AHCI3_0x30 (0xf738d2b0) = 0x4050000 AHCI3_0x34 (0xf738d2b4) = 0x0 AHCI3_0x38 (0xf738d2b8) = 0x0 AHCI3_0x3c (0xf738d2bc) = 0x0 imp: 0xf & 0x1 AtapiChipInit: dev 0xffffffff, ph chan 0, c 0 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 0 WriteChannelPort4 0 => ch0[14] UniataAhciHardReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 40e017 WriteChannelPort4 40e016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 final CMD 0x406016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x49 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 TFD 0x150 AHCI port 0 Base: 0xf738d100 MemIo 1 Proc 0 AHCI0_0x0 (0xf738d100) = 0x27cca000 AHCI0_0x4 (0xf738d104) = 0x0 AHCI0_0x8 (0xf738d108) = 0x27cca400 AHCI0_0xc (0xf738d10c) = 0x0 AHCI0_0x10 (0xf738d110) = 0x0 AHCI0_0x14 (0xf738d114) = 0x0 AHCI0_0x18 (0xf738d118) = 0x406016 AHCI0_0x1c (0xf738d11c) = 0x0 AHCI0_0x20 (0xf738d120) = 0x150 AHCI0_0x24 (0xf738d124) = 0x101 AHCI0_0x28 (0xf738d128) = 0x133 AHCI0_0x2c (0xf738d12c) = 0x300 AHCI0_0x30 (0xf738d130) = 0x0 AHCI0_0x34 (0xf738d134) = 0x0 AHCI0_0x38 (0xf738d138) = 0x0 AHCI0_0x3c (0xf738d13c) = 0x0 ReadChannelPort4 ch0[24] = 101 sig: 0x101 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch0[18] ReadChannelPort4 ch0[18] = 40e017 WriteChannelPort4 f900003f => ch0[14] check PM UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 40e017 WriteChannelPort4 40e016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 final CMD 0x406016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 final CMD 0x402006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 402006 WriteChannelPort4 40200e => ch0[18] ReadChannelPort4 ch0[18] = 402006 final CMD 0x402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch0[18] ReadChannelPort4 ch0[18] = 40e017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 406017 WriteChannelPort4 406016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 final CMD 0x406016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 final CMD 0x402006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 402006 WriteChannelPort4 40200e => ch0[18] ReadChannelPort4 ch0[18] = 402006 final CMD 0x402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch0[18] ReadChannelPort4 ch0[18] = 40e017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb71232f4, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 0 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x49, data b71232f4, count 200, lCh 0, dev 0 get Phys(AHCI_CMD=b711f080) AtapiVirtToPhysAddr_: b711f080 -> 00000000:27ccf080 get Phys(data[0]=b71232f4) AtapiVirtToPhysAddr_: b71232f4 -> 00000000:27cd32f4 set TERM ph data[0]=0:27cd32f4 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x1, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 2 IS 0x2 WriteChannelPort4 2 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 IssueIdentify: Status after read words 0x50 Model: DW CDW01PJXV2-J23C0T FW: 100. S/N: W -DXW1E1A457EL1 Pio: 0 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 4c, CAPs 0xff0e OrigTransferMode: 49, Active: 49 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x6003, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 5400 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x3fe UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x1d9265 NativeNumOfSectors 0x74706db0 Update NumOfSectors to 0x74706db0 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 NativeNumOfSectors 0x74706daf 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x1d9265 cylinders /= 2 cylinders /= 2 cylinders /= 2 (2) cylinders /= 2 (2) cylinders /= 2 (2) Use GEOM_UNIATA, CHS=ec93/80/fc Geometry: C 0xec93 (0xec93) Geometry: H 0x80 (0x80) Geometry: S 0xfc (0xfc) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb711d000 S/N:WDC_WD10JPVX-22JC3T0____________________-_____WD-WXE1A154E71L IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xf & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x0, dev 0 AtapiDisableInterrupts_0: 0 WriteChannelPort4 0 => ch0[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 49 AtaSetTransferMode: Set 0x49 on Device 0/0 AtapiDisableInterrupts_0: 1 WriteChannelPort4 0 => ch0[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x0 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 0 [0x0] Srb 0xb71244a0, AtaReq 0xb711f000, CMD 0xb711f080 ph 27ccf080 AHCI setup FIS b711f080, ch 0, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 0, AtaReq 0xb711f000 AHCI AtaReq CMD 0xb711f080 (ph 0x27ccf080) prd_length 0x0, flags 0x5, base 27ccf080 ReadChannelPort4 ch0[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch0[38] No CMD START, already active ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 1 IS 0x1 WriteChannelPort4 1 => ch0[10] UniataAhciStatus(0-0): hIS 0x0 UniataAhciEndTransaction: lChan 0 ReadChannelPort4 ch0[20] = 50 TFD 0x50 ReadChannelPort4 ch0[34] = 0 ReadChannelPort4 ch0[38] = 0 imp: 0xf & 0x1 AtapiEnableInterrupts_0: 2 WriteChannelPort4 0 => ch0[14] Using 0x49 mode imp: 0xf & 0x1 AtapiEnableInterrupts_0: 1 WriteChannelPort4 fd4000ff => ch0[14] AtapiHwInitialize: lChannel 0x0, dev 1 imp: 0xf & 0x2 AtapiChipInit: dev 0xffffffff, ph chan 1, c 1 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 1 WriteChannelPort4 0 => ch1[14] UniataAhciHardReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 40e017 WriteChannelPort4 40e016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 final CMD 0x406016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 TFD 0x150 AHCI port 1 Base: 0xf738d180 MemIo 1 Proc 0 AHCI1_0x0 (0xf738d180) = 0x27cc8000 AHCI1_0x4 (0xf738d184) = 0x0 AHCI1_0x8 (0xf738d188) = 0x27cc8400 AHCI1_0xc (0xf738d18c) = 0x0 AHCI1_0x10 (0xf738d190) = 0x0 AHCI1_0x14 (0xf738d194) = 0x0 AHCI1_0x18 (0xf738d198) = 0x406016 AHCI1_0x1c (0xf738d19c) = 0x0 AHCI1_0x20 (0xf738d1a0) = 0x150 AHCI1_0x24 (0xf738d1a4) = 0x101 AHCI1_0x28 (0xf738d1a8) = 0x123 AHCI1_0x2c (0xf738d1ac) = 0x300 AHCI1_0x30 (0xf738d1b0) = 0x0 AHCI1_0x34 (0xf738d1b4) = 0x0 AHCI1_0x38 (0xf738d1b8) = 0x0 AHCI1_0x3c (0xf738d1bc) = 0x0 ReadChannelPort4 ch1[24] = 101 sig: 0x101 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch1[18] ReadChannelPort4 ch1[18] = 40e017 WriteChannelPort4 f900003f => ch1[14] check PM UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 40e017 WriteChannelPort4 40e016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 final CMD 0x406016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406006 => ch1[18] ReadChannelPort4 ch1[18] = 402006 final CMD 0x402006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 402006 WriteChannelPort4 40200e => ch1[18] ReadChannelPort4 ch1[18] = 402006 final CMD 0x402006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch1[18] ReadChannelPort4 ch1[18] = 40e017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_1: 0 WriteChannelPort4 0 => ch1[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 406017 WriteChannelPort4 406016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 final CMD 0x406016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406006 => ch1[18] ReadChannelPort4 ch1[18] = 402006 final CMD 0x402006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 402006 WriteChannelPort4 40200e => ch1[18] ReadChannelPort4 ch1[18] = 402006 final CMD 0x402006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch1[18] ReadChannelPort4 ch1[18] = 40e017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb71232f4, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 0 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b71232f4, count 200, lCh 1, dev 0 get Phys(AHCI_CMD=b7120080) AtapiVirtToPhysAddr_: b7120080 -> 00000000:27cd0080 get Phys(data[0]=b71232f4) AtapiVirtToPhysAddr_: b71232f4 -> 00000000:27cd32f4 set TERM ph data[0]=0:27cd32f4 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x1, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 2 IS 0x2 WriteChannelPort4 2 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iTH5S5450B0A9 FW: BPO4 S/N: 111042BP4N3071P1S4EH Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 1/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 5400 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x29, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0xec93d NativeNumOfSectors 0x3a386030 Update NumOfSectors to 0x3a386030 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 NativeNumOfSectors 0x3a38602f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0xec93d Use GEOM_STD, CHS=ed81/ff/3f Geometry: C 0xed81 (0xed81) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb711d630 S/N:Hitachi_HTS545050B9A300_________________-110124PBN403171P4SHE IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xf & 0x2 AtapiEnableInterrupts_1: 1 WriteChannelPort4 fd4000ff => ch1[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x1, dev 0 AtapiDisableInterrupts_1: 0 WriteChannelPort4 0 => ch1[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 1/0 AtapiDisableInterrupts_1: 1 WriteChannelPort4 0 => ch1[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x1 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 1 [0x0] Srb 0xb71244e0, AtaReq 0xb7120000, CMD 0xb7120080 ph 27cd0080 AHCI setup FIS b7120080, ch 1, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 1, AtaReq 0xb7120000 AHCI AtaReq CMD 0xb7120080 (ph 0x27cd0080) prd_length 0x0, flags 0x5, base 27cd0080 ReadChannelPort4 ch1[18] = 406017 CMD 0x406017 Set CI WriteChannelPort4 1 => ch1[38] No CMD START, already active ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 1 IS 0x1 WriteChannelPort4 1 => ch1[10] UniataAhciStatus(1-1): hIS 0x0 UniataAhciEndTransaction: lChan 1 ReadChannelPort4 ch1[20] = 50 TFD 0x50 ReadChannelPort4 ch1[34] = 0 ReadChannelPort4 ch1[38] = 0 imp: 0xf & 0x2 AtapiEnableInterrupts_1: 2 WriteChannelPort4 0 => ch1[14] Using 0x48 mode imp: 0xf & 0x2 AtapiEnableInterrupts_1: 1 WriteChannelPort4 fd4000ff => ch1[14] AtapiHwInitialize: lChannel 0x1, dev 1 imp: 0xf & 0x4 AtapiChipInit: dev 0xffffffff, ph chan 2, c 2 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 2 WriteChannelPort4 0 => ch2[14] UniataAhciHardReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x48 UniataSataConnect: OK, ATA status 0x50 UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 150 TFD 0x150 TFD 0x150 AHCI port 2 Base: 0xf738d200 MemIo 1 Proc 0 AHCI2_0x0 (0xf738d200) = 0x27cc6000 AHCI2_0x4 (0xf738d204) = 0x0 AHCI2_0x8 (0xf738d208) = 0x27cc6400 AHCI2_0xc (0xf738d20c) = 0x0 AHCI2_0x10 (0xf738d210) = 0x0 AHCI2_0x14 (0xf738d214) = 0x0 AHCI2_0x18 (0xf738d218) = 0x404016 AHCI2_0x1c (0xf738d21c) = 0x0 AHCI2_0x20 (0xf738d220) = 0x150 AHCI2_0x24 (0xf738d224) = 0x101 AHCI2_0x28 (0xf738d228) = 0x123 AHCI2_0x2c (0xf738d22c) = 0x300 AHCI2_0x30 (0xf738d230) = 0x0 AHCI2_0x34 (0xf738d234) = 0x0 AHCI2_0x38 (0xf738d238) = 0x0 AHCI2_0x3c (0xf738d23c) = 0x0 ReadChannelPort4 ch2[24] = 101 sig: 0x101 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 f900003f => ch2[14] check PM UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 40c017 WriteChannelPort4 40c016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0x101 ATA dev FindDevices: AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 123 AHCI check ReadChannelPort4 ch2[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for IDE. Status (0x50) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xec, lba 0x0 bcount 0x0 feature 0x0, buff 0xb71232f4, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 0 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x48, data b71232f4, count 200, lCh 2, dev 0 get Phys(AHCI_CMD=b7121080) AtapiVirtToPhysAddr_: b7121080 -> 00000000:27cd1080 get Phys(data[0]=b71232f4) AtapiVirtToPhysAddr_: b71232f4 -> 00000000:27cd32f4 set TERM ph data[0]=0:27cd32f4 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x1, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 2 IS 0x2 WriteChannelPort4 2 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 IssueIdentify: Status after read words 0x50 Model: iHathc iDH7P5220G5AL FW: MGO2 S/N: EG2K03BRESSPAP Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 40/7f SATA: 40 SATA support: 5e, CAPs 0x1706 OrigTransferMode: 48, Active: 48 Accoustic 128, cur 128 AdvPowerMode 0 PowerMngt 1/1, APM 0/1 PhysLogSectorSize 0x0, 0x0, offset 0x0 NV PM_Sup 0, PM_En 0, En 0, PM ver 0x0 ver 0x0 R-rate 7200 WC 1/1, LA 1/1, WB 1/1, RB 1/1, Q 0/0 Protected 1/1 status 0x9, rev 0xfffe CHS 0x3fff:0x10:0x3f NumOfSectors 0xfbfc10 NumberOfCylinders == 0x3fff cylinders 0x41041 NumOfSectors 0xffffff0 SupportLba flag 0x1 SupportDMA flag 0x1 SoftReset 0x0 SupportIordy 0x1, DisableIordy 0x1 MajorRevision 0x1fc UserAddressableSectors 0xfffffff LBA mode LBA48 cylinders 0x764a9 NativeNumOfSectors 0x1d1c5970 Update NumOfSectors to 0x1d1c5970 Use IDE_COMMAND_READ_NATIVE_SIZE48 AtaCommand48: cntrlr 0x0:0x0 dev 0x0, cmd 0x27, lba 0x0 count 0x0 feature 0x0 (ahci) UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0x27, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x3 BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 NativeNumOfSectors 0x1d1c596f 2TB threshold, force LBA64 WRITE requirement requested LunExt->GeomType=ffffffff tmp_cylinders = 0x764a9 Use GEOM_STD, CHS=76c1/ff/3f Geometry: C 0x76c1 (0x76c1) Geometry: H 0xff (0xff) Geometry: S 0x3f (0x3f) IssueIdentify: DWORDIO supported InitBadBlocks local LunExt 0xb711dc60 S/N:Hitachi_HDP725025GLA380_________________-______GEK230RBSEPSPA IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: hard drive. IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xf & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x2, dev 0 AtapiDisableInterrupts_2: 0 WriteChannelPort4 0 => ch2[14] AtapiHwInitialize: IDE branch UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xc6, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 AtapiHwInitialize: Using Multiblock on Device 0. Blocks / int - 0 Try Enable Read Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0xaa, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 Try Enable Write Cache UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x0 feature 0x2, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 Try Enable Adv. Power Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x5, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 Try Enable Acoustic Mgmt UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x80 feature 0x42, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 Try init standby timer: 0 UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xe3, lba 0x0 bcount 0x0 feature 0x0, buff 0x0, len 0x0, WF 0x8 BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 48 AtaSetTransferMode: Set 0x48 on Device 2/0 AtapiDisableInterrupts_2: 1 WriteChannelPort4 0 => ch2[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x2 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 2 [0x0] Srb 0xb7124520, AtaReq 0xb7121000, CMD 0xb7121080 ph 27cd1080 AHCI setup FIS b7121080, ch 2, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 2, AtaReq 0xb7121000 AHCI AtaReq CMD 0xb7121080 (ph 0x27cd1080) prd_length 0x0, flags 0x5, base 27cd1080 ReadChannelPort4 ch2[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch2[38] No CMD START, already active ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 1 IS 0x1 WriteChannelPort4 1 => ch2[10] UniataAhciStatus(2-2): hIS 0x0 UniataAhciEndTransaction: lChan 2 ReadChannelPort4 ch2[20] = 50 TFD 0x50 ReadChannelPort4 ch2[34] = 0 ReadChannelPort4 ch2[38] = 0 imp: 0xf & 0x4 AtapiEnableInterrupts_2: 2 WriteChannelPort4 0 => ch2[14] Using 0x48 mode imp: 0xf & 0x4 AtapiEnableInterrupts_2: 1 WriteChannelPort4 fd4000ff => ch2[14] AtapiHwInitialize: lChannel 0x2, dev 1 imp: 0xf & 0x8 AtapiChipInit: dev 0xffffffff, ph chan 3, c 3 HwFlags: 0x12000000 VendorID/DeviceID/Rev 0x1022/0x7901/0x51 AHCI single channel init UniataAhciReset: lChan 3 WriteChannelPort4 0 => ch3[14] UniataAhciHardReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataSataPhyEnable: SControl 0x0 UniataSataPhyEnable: retry init 0 SControl 00000001 UniataSataPhyEnable: retry idle 0 SControl 00000300 UniataSataConnect: SATA TransferMode 0x47 UniataSataConnect: OK, ATA status 0x0 UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 100 TFD 0x100 TFD 0x100 AHCI port 3 Base: 0xf738d280 MemIo 1 Proc 0 AHCI3_0x0 (0xf738d280) = 0x27cc4000 AHCI3_0x4 (0xf738d284) = 0x0 AHCI3_0x8 (0xf738d288) = 0x27cc4400 AHCI3_0xc (0xf738d28c) = 0x0 AHCI3_0x10 (0xf738d290) = 0x0 AHCI3_0x14 (0xf738d294) = 0x0 AHCI3_0x18 (0xf738d298) = 0x404016 AHCI3_0x1c (0xf738d29c) = 0x0 AHCI3_0x20 (0xf738d2a0) = 0x100 AHCI3_0x24 (0xf738d2a4) = 0xeb140101 AHCI3_0x28 (0xf738d2a8) = 0x113 AHCI3_0x2c (0xf738d2ac) = 0x300 AHCI3_0x30 (0xf738d2b0) = 0x0 AHCI3_0x34 (0xf738d2b4) = 0x0 AHCI3_0x38 (0xf738d2b8) = 0x0 AHCI3_0x3c (0xf738d2bc) = 0x0 ReadChannelPort4 ch3[24] = eb140101 sig: 0xeb140101 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 f900003f => ch3[14] check PM UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 40c017 WriteChannelPort4 40c016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 signature 0xeb140101 ATAPI dev FindDevices: AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] max_ldev 1 CheckDevice: Device 0x0 SStatus 113 AHCI check ReadChannelPort4 ch3[24] = eb140101 ATAPI at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 3 UniataAhciStop: lChan 3 ReadChannelPort4 ch3[18] = 404017 WriteChannelPort4 404016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 3 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 3 send CLO ReadChannelPort4 ch3[18] = 400006 WriteChannelPort4 40000e => ch3[18] ReadChannelPort4 ch3[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 3 ReadChannelPort4 ch3[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch3[18] ReadChannelPort4 ch3[18] = 404016 UniataAhciStart: lChan 3 ReadChannelPort4 ch3[10] = 0 WriteChannelPort4 0 => ch3[10] SError 0x0, IS 0x0 ReadChannelPort4 ch3[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch3[18] ReadChannelPort4 ch3[18] = 40c017 UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciSendCommand: lChan 3 WriteChannelPort4 1 => ch3[38] ReadChannelPort4 ch3[38] = 1 ReadChannelPort4 ch3[10] = 0 ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 0 IS 0x0 WriteChannelPort4 0 => ch3[10] UniataAhciWaitReady: lChan 3 ReadChannelPort4 ch3[20] = 100 TFD 0x100 34 00 00 01 01 14 eb 00 00 00 00 00 01 00 00 00 00 00 00 00 IssueIdentify: Checking for ATAPI. Status (0x0) UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xa1, lba 0x0 bcount 0x0 feature 0x0, buff 0xb71232f4, len 0x200, WF 0x2 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7124560, AtaReq 0xb7122000, CMD 0xb7122080 ph 0 AHCI setup FIS b7122080, ch 3, dev 0 ahci_flags 0x5 assume IN AtapiDmaSetup: mode 0x47, data b71232f4, count 200, lCh 3, dev 0 get Phys(AHCI_CMD=b7122080) AtapiVirtToPhysAddr_: b7122080 -> 00000000:27cd2080 get Phys(data[0]=b71232f4) AtapiVirtToPhysAddr_: b71232f4 -> 00000000:27cd32f4 set TERM ph data[0]=0:27cd32f4 (1ff) AtapiDmaSetup: OK UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7122000 AHCI AtaReq CMD 0xb7122080 (ph 0x27cd2080) prd_length 0x1, flags 0x5, base 27cd2080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 2 IS 0x2 WriteChannelPort4 2 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 IssueIdentify: Status after read words 0x50 Model: LHD--TTSB -DER HB61 FW: .120 S/N: IS9KHIK33E47 Pio: 2 APio: 3 SWDMA: 0 MWDMA: 0 UDMA: 20/7f SATA: 40 SATA support: 60, CAPs 0x402 OrigTransferMode: 47, Active: 47 Accoustic 0, cur 0 AdvPowerMode 0 PowerMngt 0/0, APM 0/0 AtapiByteCount0=2000 InitBadBlocks local LunExt 0xb711e290 S/N:HL-DT-ST_BD-RE__BH16NS55________________-SIK9IH3KE374________ IssueIdentify: Device does not interrupt on assertion of DRQ. IssueIdentify: Device is CD/Optical drive. IssueIdentify: AtapiCmdSize 0x0 IssueIdentify: final Status on exit (0x50) CheckDevice: detected AHCI Device 0x0 CheckDevice: check status: found imp: 0xf & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] FindDevices: returning 1 (AHCI) AtapiHwInitialize: lChannel 0x3, dev 0 AtapiDisableInterrupts_3: 0 WriteChannelPort4 0 => ch3[14] AtapiHwInitialize: ATAPI/Changer branch try mode 0x49 AtapiDmaInit__: Set (U)DMA on Device 0 AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA AtapiDmaInit: LunExt->LimitedTransferMode 0x49 AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => 0x6 SATA Generic LunExt->LimitedTransferMode 49, LunExt->OrigTransferMode 47 AtaSetTransferMode: Set 0x47 on Device 3/0 AtapiDisableInterrupts_3: 1 WriteChannelPort4 0 => ch3[14] UniataAhciSendPIOCommand: cntrlr 0x0:0x3 dev 0x0, cmd 0xef, lba 0x0 bcount 0x46 feature 0x3, buff 0x0, len 0x0, WF 0x8 length/DEV_BSIZE != bcount BuildAhciInternalSrb: lChan 3 [0x0] Srb 0xb7124560, AtaReq 0xb7122000, CMD 0xb7122080 ph 27cd2080 AHCI setup FIS b7122080, ch 3, dev 0 ahci_flags 0x5 UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7122000 AHCI AtaReq CMD 0xb7122080 (ph 0x27cd2080) prd_length 0x0, flags 0x5, base 27cd2080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 Set CI WriteChannelPort4 1 => ch3[38] No CMD START, already active ReadChannelPort4 ch3[38] = 0 CI 0x0 ReadChannelPort4 ch3[10] = 1 IS 0x1 WriteChannelPort4 1 => ch3[10] UniataAhciStatus(3-3): hIS 0x0 UniataAhciEndTransaction: lChan 3 ReadChannelPort4 ch3[20] = 50 TFD 0x50 ReadChannelPort4 ch3[34] = 0 ReadChannelPort4 ch3[38] = 0 imp: 0xf & 0x8 AtapiEnableInterrupts_3: 2 WriteChannelPort4 0 => ch3[14] Using 0x47 mode imp: 0xf & 0x8 AtapiEnableInterrupts_3: 1 WriteChannelPort4 fd4000ff => ch3[14] AtapiHwInitialize: lChannel 0x3, dev 1 AtapiHwInitialize: (base) done TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x1 SRB 0xf7401380, CDB 0xf74013b0, AtaReq 0xb7103000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf7401150 ** Ide: Command AtaReq 0xb7103000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x0:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf7401380 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b711c008, f7401380) AtapiStartIo: UniataRemoveRequest(b711c008, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b711c008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request (drivers/storage/port/scsiport/fdo.c:326) SCSIPORT: created lun device: B7100038 Status: 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf7401380 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x0:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x1 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 133 AHCI check ReadChannelPort4 ch0[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 0 UniataAhciStop: lChan 0 ReadChannelPort4 ch0[18] = 406017 WriteChannelPort4 406016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 final CMD 0x406016 UniataAhciStopFR: lChan 0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406006 => ch0[18] ReadChannelPort4 ch0[18] = 402006 final CMD 0x402006 UniataAhciCLO: lChan 0 send CLO ReadChannelPort4 ch0[18] = 402006 WriteChannelPort4 40200e => ch0[18] ReadChannelPort4 ch0[18] = 402006 final CMD 0x402006 UniataAhciStartFR: lChan 0 ReadChannelPort4 ch0[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch0[18] ReadChannelPort4 ch0[18] = 406016 UniataAhciStart: lChan 0 ReadChannelPort4 ch0[10] = 0 WriteChannelPort4 0 => ch0[10] SError 0x0, IS 0x0 ReadChannelPort4 ch0[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch0[18] ReadChannelPort4 ch0[18] = 40e017 UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciSendCommand: lChan 0 WriteChannelPort4 1 => ch0[38] ReadChannelPort4 ch0[38] = 1 ReadChannelPort4 ch0[10] = 0 ReadChannelPort4 ch0[38] = 0 CI 0x0 ReadChannelPort4 ch0[10] = 0 IS 0x0 WriteChannelPort4 0 => ch0[10] UniataAhciWaitReady: lChan 0 ReadChannelPort4 ch0[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf7401380 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b711c008, f7401380) AtapiStartIo: UniataRemoveRequest(b711c008, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b711c008, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x2 SRB 0xf7401380, CDB 0xf74013b0, AtaReq 0xb7103000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf7401150 ** Ide: Command AtaReq 0xb7103000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x1:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf7401380 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b711c268, f7401380) AtapiStartIo: UniataRemoveRequest(b711c268, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b711c268, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request (drivers/storage/port/scsiport/fdo.c:326) SCSIPORT: created lun device: B70FFA08 Status: 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf7401380 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x1:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x2 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 SStatus 123 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 123 AHCI check ReadChannelPort4 ch1[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 1 UniataAhciStop: lChan 1 ReadChannelPort4 ch1[18] = 406017 WriteChannelPort4 406016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 final CMD 0x406016 UniataAhciStopFR: lChan 1 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406006 => ch1[18] ReadChannelPort4 ch1[18] = 402006 final CMD 0x402006 UniataAhciCLO: lChan 1 send CLO ReadChannelPort4 ch1[18] = 402006 WriteChannelPort4 40200e => ch1[18] ReadChannelPort4 ch1[18] = 402006 final CMD 0x402006 UniataAhciStartFR: lChan 1 ReadChannelPort4 ch1[18] = 402006 CMD 0x402006 WriteChannelPort4 402016 => ch1[18] ReadChannelPort4 ch1[18] = 406016 UniataAhciStart: lChan 1 ReadChannelPort4 ch1[10] = 0 WriteChannelPort4 0 => ch1[10] SError 0x0, IS 0x0 ReadChannelPort4 ch1[18] = 406016 CMD 0x406016 WriteChannelPort4 406017 => ch1[18] ReadChannelPort4 ch1[18] = 40e017 UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciSendCommand: lChan 1 WriteChannelPort4 1 => ch1[38] ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 1 ReadChannelPort4 ch1[10] = 0 ReadChannelPort4 ch1[38] = 0 CI 0x0 ReadChannelPort4 ch1[10] = 0 IS 0x0 WriteChannelPort4 0 => ch1[10] UniataAhciWaitReady: lChan 1 ReadChannelPort4 ch1[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf7401380 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b711c268, f7401380) AtapiStartIo: UniataRemoveRequest(b711c268, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b711c268, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x4 SRB 0xf7401380, CDB 0xf74013b0, AtaReq 0xb7103000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 Try IDE send ** Ide: Command: entryway ** Ide: Command: ** Ide: Command &AtaReq 0xf7401150 ** Ide: Command AtaReq 0xb7103000 ** --- ** IdeSendCommand: SCSIOP_INQUIRY PATH:LUN:TID = 0x2:0x0:0x0 IdeSendCommand: SCSIOP_INQUIRY ok SStatus 123 AHCI check ReadChannelPort4 ch2[24] = 101 AHCI HDD at home RelativeAddressing IdeSendCommand: REQ_STATE_TRANSFER_COMPLETE AtapiStartIo: Srb 0xf7401380 complete with status 0x1 AtapiStartIo: AtapiDmaDBSync(b711c4c8, f7401380) AtapiStartIo: UniataRemoveRequest(b711c4c8, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b711c4c8, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request (drivers/storage/port/scsiport/fdo.c:326) SCSIPORT: created lun device: B70FD038 Status: 0 TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x1:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf7401380 complete with status 0xa AtapiStartIo: UniataRemoveRequest(0, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan 0, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x2:0x0:0x1 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x4 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 SStatus 123 AHCI check ReadChannelPort4 ch2[24] = 101 AHCI HDD at home CheckDevice: Device 0x1 SStatus 123 AHCI check ReadChannelPort4 ch2[24] = 101 AHCI HDD at home CheckDevice: reset AHCI dev UniataAhciSoftReset: lChan 2 UniataAhciStop: lChan 2 ReadChannelPort4 ch2[18] = 404017 WriteChannelPort4 404016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 final CMD 0x404016 UniataAhciStopFR: lChan 2 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404006 => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciCLO: lChan 2 send CLO ReadChannelPort4 ch2[18] = 400006 WriteChannelPort4 40000e => ch2[18] ReadChannelPort4 ch2[18] = 400006 final CMD 0x400006 UniataAhciStartFR: lChan 2 ReadChannelPort4 ch2[18] = 400006 CMD 0x400006 WriteChannelPort4 400016 => ch2[18] ReadChannelPort4 ch2[18] = 404016 UniataAhciStart: lChan 2 ReadChannelPort4 ch2[10] = 0 WriteChannelPort4 0 => ch2[10] SError 0x0, IS 0x0 ReadChannelPort4 ch2[18] = 404016 CMD 0x404016 WriteChannelPort4 404017 => ch2[18] ReadChannelPort4 ch2[18] = 40c017 UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciSendCommand: lChan 2 WriteChannelPort4 1 => ch2[38] ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 1 ReadChannelPort4 ch2[10] = 0 ReadChannelPort4 ch2[38] = 0 CI 0x0 ReadChannelPort4 ch2[10] = 0 IS 0x0 WriteChannelPort4 0 => ch2[10] UniataAhciWaitReady: lChan 2 ReadChannelPort4 ch2[20] = 150 TFD 0x150 34 00 50 01 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 CheckDevice: check status: not found AtapiStartIo: SRB rejected SRB_STATUS_SELECTION_TIMEOUT AtapiStartIo: Srb 0xf7401380 complete with status 0xa AtapiStartIo: AtapiDmaDBSync(b711c4c8, f7401380) AtapiStartIo: UniataRemoveRequest(b711c4c8, f7401380) AtapiStartIo: ScsiPortNotification AtapiStartIo: UniataGetCurRequest AtapiStartIo: chan b711c4c8, Src 0 AtapiStartIo: next Srb 0 AtapiStartIo: query PORT for next request TopLevel ** AtapiStartIo: Function 0x0, PATH:LUN:TID = 0x3:0x0:0x0 DeviceID+VendorID/Rev 0x79011022/0x51 imp: 0xf & 0x8 SRB 0xf7401380, CDB 0xf74013b0, AtaReq 0xb7103000, SCmd 0x12 UniataNeedQueueing: TopLevel, qd=0 Send to device 12 TopLevel (2), srb 0xf7401380 TopLevel (3), AtaReq 0xb7103000 Try ATAPI send 12 AtapiSendCommand: req state 0x10, Action 3 AtapiSendCommand: prepare..., ATAPI CMD 12 (Cdb f74013b0) assume IN AtapiSendCommand: force use dma (ahci) AtapiSendCommand: use dma (ahci) AtaReq 0xb7103000: cmd aligned b7103080, d=20 ahci_cmd_ptr 0xb7103080 AtapiDmaSetup: mode 0x47, data f738c9a0, count 24, lCh 3, dev 0 get Phys(AHCI_CMD=b7103080) AtapiVirtToPhysAddr_: b7103080 -> 00000000:27cb3080 get Phys(data[0]=f738c9a0) AtapiVirtToPhysAddr_: f738c9a0 -> 00000000:2832b9a0 set TERM ph data[0]=0:2832b9a0 (23) AtapiDmaSetup: OK AtapiSendCommand: setup AHCI FIS AHCI setup FIS b7103080, ch 3, dev 0 AtapiSendCommand ahci io flags a5: AtapiSendCommand: use_dma=1, Cmd 12 REQ_FLAG_DMA_OPERATION AtapiSendCommand: AtapiDmaReinit() AtapiDmaReinit: LimitedTransferMode == TransferMode = 47 (3), Device 0, last dev 0 AtapiSendCommand: use_dma=1 REQ_FLAG_DMA_OPERATION AtapiSendCommand: CMD_ACTION_EXEC AtapiSendCommand: Cdb f74013b0 Command 0x12 to TargetId 0 lun 0 AtapiSendCommand: Entered with status 0x50 ReadChannelPort4 ch3[38] = 0 AtapiSendCommand: AHCI, begin transaction UniataAhciBeginTransaction: lChan 3, AtaReq 0xb7103000 AHCI AtaReq CMD 0xb7103080 (ph 0x27cb3080) prd_length 0x1, flags 0xa5, base 27cb3080 ReadChannelPort4 ch3[18] = 404017 CMD 0x404017 ATAPI 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00 send CMD 0x1404017, entries 0x1 WriteChannelPort4 1404017 => ch3[18] ReadChannelPort4 ch3[18] = 140c017 Set CI WriteChannelPort4 1 => ch3[38] Send CMD START (0x1404017 != 0x140c017) WriteChannelPort4 1404017 => ch3[18] ReadChannelPort4 ch3[18] = 140c017 AtapiStartIo: next Srb f7401380 AtapiStartIo: query PORT for next request c